fish fry
Subscribe Now

Autonomous Driving in the Fast Lane: The Growing Need for an Architectural Redefinition of Computation Hardware

Autonomous driving takes center stage in this week’s Fish Fry podcast! Steven Latré from imec and I are talking all about SWIR, lidar, mm-wave radar, sensor fusion, the growing need for architectural redefinition of computation hardware in autonomous driving and a whole lot more!


Links for October 13, 2023

More information about upcoming ITF Worlds

More information about AI technology at imec 

More information about automotive technologies at imec 

Steven Latré LinkedIn

Fish Fry podcast interview with Jo De Boeck (imec)

Click here to check out the Fish Fry Archive.

Click here to subscribe to Fish Fry via Podbean

Click here to get the Fish Fry RSS Feed

Click here to subscribe to Fish Fry via Apple Podcasts

Click here to subscribe to Fish Fry via Spotify

 

Fish Fry Executive Interviews

David Mayman, CEO – Mayman Aerospace 

Anupam Bakshi, CEO – Agnisys

Dave Kleidermacher, CTO – Green Hills Software

Robert Blake, CEO – Achronix

Jack Harding, CEO – eSilicon

Michiel Ligthart, COO – Verific

Simon Davidmann, CEO – Imperas

Jessica Gomez – Rogue Valley Microdevices

Shishpal Rawat, Chairman – Accellera Systems Initiative

Kevin Bromber, CEO – myDevices

Daniel Hansson, CEO – Verifyter

Mark Papermaster, CTO – AMD

David Fried, CTO – Coventor

Dr. Steven LeBoeuf, President – Valencell

David Dutton, CEO – Silvaco

Bob Niemiec, CEO – TwistThink

Allan Martinson, COO – Starship Technologies

Zhihong Liu, Chairman and CEO – ProPlus Solutions

Taher Madraswala, CEO and President – Open-Silicon

Kapil Shankar, CEO and Director – AnDAPT

Dan Fox, CTO – Local Motors

Kim Rowe, Founder and CEO — RoweBots

Lawrence Cooke, Founder and CEO — NovaSolix

Gregg Recupero, CTO — Performance-IP

Alan Grau, CEO — Icon Labs

Carl Alberty, Vice President – Cirrus Logic

Maximilian Odendahl, CEO — Silexica

Finbarr Moynihan, General Manager — MediaTek

Sanjay Pillay, CEO — Austemper

Louis Parks, CEO – SecureRF

Harold Blomquist, CEO – Helix Semiconductor

Dale Dougherty and Sherry Huss, Co-Founders – Maker Faire

David Su, CEO – Atomic Technologies

Mung Chiang, EVP and Dean of Engineering College – Purdue University

Clay Johnson, CEO – CacheQ

Andy Hock, Vice President, Product – Cerebras Systems

Dan Goehl, Co-founder and Chief Business Officer – UltraSense Systems

Charlie Green, Chief Operating & Technical Officer – Powercast

One thought on “Autonomous Driving in the Fast Lane: The Growing Need for an Architectural Redefinition of Computation Hardware”

  1. Is there a discussion group for new processor architecture? I would like to join since my career was in computer and system design and architecture and have a new approach to discuss.

Leave a Reply

featured blogs
Dec 8, 2023
Read the technical brief to learn about Mixed-Order Mesh Curving using Cadence Fidelity Pointwise. When performing numerical simulations on complex systems, discretization schemes are necessary for the governing equations and geometry. In computational fluid dynamics (CFD) si...
Dec 7, 2023
Explore the different memory technologies at the heart of AI SoC memory architecture and learn about the advantages of SRAM, ReRAM, MRAM, and beyond.The post The Importance of Memory Architecture for AI SoCs appeared first on Chip Design....
Nov 6, 2023
Suffice it to say that everyone and everything in these images was shot in-camera underwater, and that the results truly are haunting....

featured video

Dramatically Improve PPA and Productivity with Generative AI

Sponsored by Cadence Design Systems

Discover how you can quickly optimize flows for many blocks concurrently and use that knowledge for your next design. The Cadence Cerebrus Intelligent Chip Explorer is a revolutionary, AI-driven, automated approach to chip design flow optimization. Block engineers specify the design goals, and generative AI features within Cadence Cerebrus Explorer will intelligently optimize the design to meet the power, performance, and area (PPA) goals in a completely automated way.

Click here for more information

featured paper

3D-IC Design Challenges and Requirements

Sponsored by Cadence Design Systems

While there is great interest in 3D-IC technology, it is still in its early phases. Standard definitions are lacking, the supply chain ecosystem is in flux, and design, analysis, verification, and test challenges need to be resolved. Read this paper to learn about design challenges, ecosystem requirements, and needed solutions. While various types of multi-die packages have been available for many years, this paper focuses on 3D integration and packaging of multiple stacked dies.

Click to read more

featured chalk talk

Littelfuse Protection IC (eFuse)
If you are working on an industrial, consumer, or telecom design, protection ICs can offer a variety of valuable benefits including reverse current protection, over temperature protection, short circuit protection, and a whole lot more. In this episode of Chalk Talk, Amelia Dalton and Pete Pytlik from Littelfuse explore the key features of protection ICs, how protection ICs compare to conventional discrete component solutions, and how you can take advantage of Littelfuse protection ICs in your next design.
May 8, 2023
27,466 views