I’m sure you know what the terms CPU, MPU, MCU, and GPU stand for. I’d wager you think you know which functional blocks each of these terms embraces. But are you 100% certain? Would you bet on it?
One of the problems we have in the electronics and computing industries is a surfeit of TLAs (three letter acronyms). The … Read More → "What the FAQ are CPUs, MPUs, MCUs, and GPUs?"
“I don’t want my personality to overshadow my talent.” – Cardi B
What is the IP business, really? You’re buying a product, albeit an intangible one. You pay a license fee and you get a thing in return, like huge and complicated Verilog files or millions of lines of software. Maybe you also get some documentation, or … Read More → "Imagination Technologies Rents Talent"
The upshot: The Tide Organization tested password splintering and, in one study, found an increase of 14,064,094% in security as compared with “conventional, centralized alternatives.”
Passwords are this horrible thing that we can’t seem to escape. If we’re doing it right, each of the 300-odd passwords we need will be random, long, changed every month, and, of … Read More → "Passwords Rent Asunder"
What do high level synthesis, FPGAs, and the first 3D printer capable of printing fully-functional electronics have in common? This week’s podcast, of course! First up, I chat with Max Odendahl (CEO, Founder – Silexica) about ins and outs of system level understanding and optimization, what we can do with unsynthesizable C/C++ code and how we can tackle the biggest challenges in using Software (C/C++) for hardware … Read More → "Driving Optimization"
In a recent Cool Beans column — What the FAQ are the IoT, IIoT, IoHT, and AIoT? – I introduced the concepts of the cloud, the fog, … Read More → "What the FAQ is the Edge vs. the Far Edge?"
In part 1 of this series, we looked at new high-end FPGA families from Xilinx, Intel, and Achronix and discussed their underlying semiconductor processes, the type and amount of programmable logic LUT fabric, the type and amount of DSP/arithmetic resources and their applicability to AI inference acceleration tasks, the claimed TOPS/FLOPS performance capabilities, and on-chip interconnect … Read More → "High-End FPGA Showdown – Part 3"
