Synopsys Takes on RISC-V Configurability with ARC-V Processor IP Family

Long, long ago, at the turn of the millennium, two champions of configurable processor IP – ARC and Tensilica – battled for dominance in that arena with unique processor ISAs and custom tools to aid in creating software-development tool chains for their configurable processors. Synopsys bought ARC in 2011, and Cadence bought Tensilica a couple of years later. Fast forward a decade and suddenly, RISC-V has somehow validated the concept … Read More → "Synopsys Takes on RISC-V Configurability with ARC-V Processor IP Family"

Extremely Low Latency FPGAs and SmartNICs: How Achronix is Supercharging Networking Innovation

FPGAs take center stage in this week’s Fish Fry podcast! But not just any field programmable gate arrays – I’m talking about the Speedster7t FPGAs! My guests Scott Schweitzer and Ron Renwick from Achronix and I chat about why Achronix’s FPGAs are particularly well suited for networking and SmartNIC tasks, the advantages of Achronix’s accelerated network infrastructure code and the details of their new FPGA-Powered … Read More → "Extremely Low Latency FPGAs and SmartNICs: How Achronix is Supercharging Networking Innovation"

9.6Gbps HBM3 Memory Controller IP Boosts SoC AI Performance

It’s not often you get to say things like “exponential increase in insatiable demand,” so I’m going to make the most of it by taking a deep breath, pausing for effect, and waiting for the audience’s antici…

…pation to mount. As I’ve mentioned in previous columns (although possibly using different words), we are currently seeing an … Read More → "9.6Gbps HBM3 Memory Controller IP Boosts SoC AI Performance"

New MCUs Provide 10^2 the Performance at 10^-2 the Power

As I’ve mentioned on occasion, I predate many of the technologies that now surround us. I remember the heady days of the first 8-bit microprocessor units (MPUs) and early single board computers (SBCs) that were based on these little rascals. Glancing at the bookshelves in my office, I see my trusty companions of yesteryear in the form of 6502, Z80, etc. data books.

Read More → "New MCUs Provide 10^2 the Performance at 10^-2 the Power"

Arrow reveals first Dev Board for Intel Agilex 5 FPGAs, with two more boards planned

Arrow has just launched a development board for Intel’s soon-to-be-produced Agilex 5 SoC FPGAs, and two more such boards wait in the wings. The Arrow AXE5-Eagle board sports one Intel Agilex 5 E-series SoC FPGA. Initially, these development boards will incorporate an engineering sample of the SoC FPGA with 656K logic elements (LEs), while production boards, available by the end of the first half of 2024, will incorporate … Read More → "Arrow reveals first Dev Board for Intel Agilex 5 FPGAs, with two more boards planned"

High Speed Communications, Optical Interfaces and the Future of Embedded Systems

This week’s podcast is all about high speed communication, optical interfaces for military and aerospace designs and 3D printing in space! My guest Patrick Mechin (Techway) and I discuss the trends in high speed communications, the benefits of optical interfaces for modern embedded systems, and how Techway is supporting innovation in this arena. Also this week, I check out how 3D-printed titanium dioxide foam could help us in … Read More → "High Speed Communications, Optical Interfaces and the Future of Embedded Systems"

December 5, 2023
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November 23, 2023

featured chalk talk

Intel AI Update
Sponsored by Mouser Electronics and Intel
In this episode of Chalk Talk, Amelia Dalton and Peter Tea from Intel explore how Intel is making AI implementation easier than ever before. They examine the typical workflows involved in artificial intelligence designs, the benefits that Intel’s scalable Xeon processor brings to AI projects, and how you can take advantage of the Intel AI ecosystem to further innovation in your next design.
Oct 6, 2023

featured webinar

Rapid Learning: Purpose-Built MCU Software Tools for Data-Driven Embedded IoT Systems

Sponsored by ITTIA

Are you developing an MCU application that captures data of all kinds (metrics, events, logs, traces, etc.)? Are you ready to reduce the difficulties and complications involved in developing an event- and data-centric embedded system? This webinar will quickly introduce you to excellent MCU-specific software options for developing your next-generation data-driven IoT systems. You will also learn how to recognize and overcome data management obstacles. Register today as seats are limited!

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featured video

Dramatically Improve PPA and Productivity with Generative AI

Sponsored by Cadence Design Systems

Discover how you can quickly optimize flows for many blocks concurrently and use that knowledge for your next design. The Cadence Cerebrus Intelligent Chip Explorer is a revolutionary, AI-driven, automated approach to chip design flow optimization. Block engineers specify the design goals, and generative AI features within Cadence Cerebrus Explorer will intelligently optimize the design to meet the power, performance, and area (PPA) goals in a completely automated way.

Click here for more information

Posted on Dec 5 at 5:33am by Steven Leibson
No Karl, these studies are not published and are considered proprietary. It's called "do your own research." As for stack-based computers, HP during its many love affairs with strange processor architectures briefly fell in love with stack-based machines and implemented the original "classic" HP 3000 minicomputer as a stack machine. As ...
Posted on Dec 3 at 11:20am by Karl Stevens
Has any of that ever been published for the general masses of idiots like me to peruse? And how are we to know that the benchmark applications they use have any resemblance to the particular application being developed? The secret sauce is to design/use a stack based computer to ...
Posted on Dec 2 at 3:38pm by Steven Leibson
I don't think that's right Karl. Processor designers did not evolve first, second, and third-level caches and multiple cache policies using wet-finger and Kentucky windage methods of engineering. Every application has a different cache hit ratio and processor designers use a basket of target applications to size caches and develop ...
Posted on Nov 30 at 8:57am by Karl Stevens
Since day one, memory access time has been critical. (because data is accessed randomly) DDR data rate is only one factor since it reduces the impact on access time for cache misses. So this just seems like "Gee, what a big number!" (in a squeaky voice, of course!) Has anyone ...
Posted on Nov 9 at 10:19am by Max Maxfield
Well -- they do work, but not well LOL
Posted on Nov 8 at 9:04pm by kimhailey
Server farms do not work with intermittent power sources.
Posted on Nov 6 at 10:34am by Max Maxfield
You pose a good question -- I can't believe I forgot to ask -- I just emailed Andreas and asked -- Max
Posted on Nov 4 at 6:58am by DaveN
Max! You haven't told us how much it will cost! Can I also retreat to the basement and build something, or will I need to mortgage the house?
Posted on Nov 3 at 10:51am by Max Maxfield
I didn't get to talk about it here -- but Macronix do have in-memory compute capability -- also a lot of folks are working on Computational SSD or Near Data Processing (NDP) where a lot of processing actually takes place in the drive. One day we will have a memory ...
Posted on Nov 2 at 2:37pm by Max Maxfield
You make a good point. With exascale computers currently coming online, each requiring its own 20MW power station, I can't imagine where we will be or what we will be doing in 10 years time (but it will be interesting to see).
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featured blogs
Dec 5, 2023
Generative AI has become a buzzword in 2023 with the explosive proliferation of ChatGPT and large language models (LLMs). This brought about a debate about which is trained on the largest number of parameters. It also expanded awareness of the broader training of models for s...
Nov 27, 2023
See how we're harnessing generative AI throughout our suite of EDA tools with Synopsys.AI Copilot, the world's first GenAI capability for chip design.The post Meet Copilot, Industry's First GenAI Capability for Chip Design appeared first on Chip Design....
Nov 6, 2023
Suffice it to say that everyone and everything in these images was shot in-camera underwater, and that the results truly are haunting....
Reliable Connections for Rugged Handling
Materials handling is a growing market for electronic designs. In this episode of Chalk Talk, Amelia Dalton and Jordan Grupe from Amphenol Industrial explore the variety of connectivity solutions that Amphenol Industrial offers for materials handling designs. They also examine the DIN charging solutions that Amphenol Industrial offers and the specific applications where these connectors can be a great fit.
Dec 5, 2023
Must be Thin to Fit: µModule Regulators
In this episode of Chalk Talk, Amelia Dalton and Younes Salami from Analog Devices explore the benefits and restrictions of Analog Devices µModule regulators. They examine how these µModule regulators can declutter PCB area and increase the system performance of your next design, and the variety of options that Analog Devices offers within their Ultrathin µModule® regulator product portfolio.
Dec 5, 2023
Using the Vishay IHLE® to Mitigate Radiated EMI
Sponsored by Mouser Electronics and Vishay
EMI mitigation is an important design concern for a lot of different electronic systems designs. In this episode of Chalk Talk, Amelia Dalton and Tim Shafer from Vishay explore how Vishay’s IHLE power inductors can reduce radiated EMI. They also examine how the composition of these inductors can support the mitigation of EMI and how you can get started using Vishay’s IHLE® High Current Inductors in your next design.
Dec 4, 2023
Power Gridlock
The power grid is struggling to meet the growing demands of our electrifying world. In this episode of Chalk Talk, Amelia Dalton and Jake Michels from YAGEO Group discuss the challenges affecting our power grids today, the solutions to help solve these issues and why passive components will be the heroes of grid modernization.
Nov 28, 2023
Achieving Reliable Wireless IoT
Sponsored by Mouser Electronics and CEL
Wireless connectivity is one of the most important aspects of any IoT design. In this episode of Chalk Talk, Amelia Dalton and Brandon Oakes from CEL discuss the best practices for achieving reliable wireless connectivity for IoT. They examine the challenges of IoT wireless connectivity, the factors engineers should keep in mind when choosing a wireless solution, and how you can utilize CEL wireless connectivity technologies in your next design.
Nov 28, 2023
Neutrik powerCON®: Twist and Latch Locking AC Power Connectors
Sponsored by Mouser Electronics and Neutrik
If your next design demands frequent connector mating and unmating and use in countries throughout the world, a twist and latch locking AC power connector would be a great addition to your system design. In this episode of Chalk Talk, Amelia Dalton and Fred Morgenstern from Neutrik explore the benefits of Neutrik's powerCON® AC power connectors, the electrical and environmental specifications included in this connector family, and why these connectors are a great fit for a variety of AV and industrial applications. 
Nov 27, 2023