EEJournal

fish fry
Subscribe Now
June 17, 2016

The Amalgamation Situation

AMD and the Era of Data Convergence
by Amelia Dalton

Keep innovation in your back pocket and the end game in your sights at all times. This race is ride or die. The data center waits for no one. Mark Papermaster (CTO – AMD) joins Fish Fry this week to discuss the complex chip competition in the data center market, why open ecosystems are the lynchpin of data center evolution, and why he believes that your product is only as good as your team.  Also this week, we take a closer look at how you can maximize your performance-per-watt with Zynq UltraScale+ MPSoCs.


 

Download this episode (right click and save)

Links for June 17, 2016

More information about AMD

New Episode of Chalk Talk: Running Out of Processing Power? No Problem.

Fish Fry Executive Interviews

Moshe Gavrielov, CEO – Xilinx

Darrin Billerbeck, CEO – Lattice Semiconductor

Bill Neifert, CTO – Carbon Design Systems

Sean Dart, CEO – Forte Design Systems

Andy Pease, CEO – QuickLogic

Paul Kocher, President – Cryptography Research Inc.

Anupam Bakshi, CEO – Agnisys

Dave Kleidermacher, CTO – Green Hills Software

Robert Blake, CEO – Achronix

Jack Harding, CEO – eSilicon

Michiel Ligthart, COO – Verific

Adnan Hamid, CEO – Breker Technologies

Jeff Waters, VP and General Manager – Altera

Simon Davidmann, CEO – Imperas

Ted Miracco, CEO – SmartFlow Compliance Solutions

Cees Links – GreenPeak Technologies

Jessica Gomez – Rogue Valley Microdevices

Shishpal Rawat, Chairman – Accellera Systems Initiative

Kevin Bromber, CEO – myDevices

Daniel Hansson, CEO – Verifyter

Leave a Reply

featured blogs
Sunday Brunch Video for 27th September 2020
Sep 27, 2020
https://youtu.be/EUDdGqdmTUU Made in "the Alps" Monday: Complete RF Solution: Think Outside the Chip Tuesday: The First Decade of RISC-V: A Worldwide Phenomenon Wednesday: The European... [[ Click on the title to access the full blog on the Cadence Community site. ...
More from Cadence...
Hands Off My Brain Data!
Sep 25, 2020
What do you think about earphone-style electroencephalography sensors that would allow your boss to monitor your brainwaves and collect your brain data while you are at work?...
More from Max\'s Cool Beans...
Samtec Dives In the Deep End with PICMG
Sep 25, 2020
Weird weather is one the things making 2020 memorable. As I look my home office window (WFH – yet another 2020 “thing”!), it feels like mid-summer in late September. In some places like Key West or Palm Springs, that is normal. In Pennsylvania, it is not. My...
More from Samtec, Inc....
Resistors for Memory Cells
Sep 25, 2020
[From the last episode: We looked at different ways of accessing a single bit in a memory, including the use of multiplexors.] Today we'€™re going to look more specifically at memory cells '€“ these things we'€™ve been calling bit cells. We mentioned that there are many...
More from Inside the IoT...

Featured Video

Product Update: PVT Monitor IP

Sponsored by Synopsys

Join Rupal Gandhi to learn about silicon-proven process monitors and voltage/temperature sensor IP from Synopsys. PVT monitors provide real-time feedback to SoC designers.

Click here for more information about DesignWare Foundation IP: Embedded Memories, Logic Libraries & GPIO

Featured Paper

The Cryptography Handbook

Sponsored by Maxim Integrated

The Cryptography Handbook is designed to be a quick study guide for a product development engineer, taking an engineering rather than theoretical approach. In this series, we start with a general overview and then define the characteristics of a secure cryptographic system. We then describe various cryptographic concepts and provide an implementation-centric explanation of physically unclonable function (PUF) technology. We hope that this approach will give the busy engineer a quick understanding of the basic concepts of cryptography and provide a relatively fast way to integrate security in his/her design.

Click here to download the whitepaper

Featured Chalk Talk

SLX FPGA: Accelerate the Journey from C/C++ to FPGA

Sponsored by Silexica

High-level synthesis (HLS) brings incredible power to FPGA design. But harnessing the full power of HLS with FPGAs can be difficult even for the most experienced engineering teams. In this episode of Chalk Talk, Amelia Dalton chats with Jordon Inkeles of Silexica about using the SLX FPGA tool to truly harness the power of HLS with FPGAs, getting better results faster - regardless of whether you are approaching from the hardware or software domain.

More information about SLX FPGA