A Billion Instances and Counting – Solving the Challenges of IC Design Closure
Integrated circuits once again take center stage in this week’s Fish Fry podcast! Brandon Bautz (Cadence Design Systems) and I chat about the challenges of IC design closure today, how distribution and optimization can help address these growing design challenges, and the details of the Cadence® Certus™ Closure Solution. Also this week I investigate a new soft robot developed by Cornell University that can detect damage and heal … Read More → "A Billion Instances and Counting – Solving the Challenges of IC Design Closure"
Automation and the Future of IC Design for Test
What do IC design for test, the Tessent multi-die software solution and the best semiconductor material of all time have in common? This week’s podcast of course! My guest Vidya Neerkundar (Siemens) and I discuss trends in the IC industry today, the unique testing challenges for today’s cutting edge integrated circuits and why automation for 2D and 3D IC design-for-test is the way of the future. Also … Read More → "Automation and the Future of IC Design for Test"
What Can One Do with an Array of 250,000 Ultrasonic Transducers?
In Memoriam: Dave Cochran, an Engineer’s Engineer
Sadly, my friend Dave Cochran passed away on October 7. You’ve likely never heard of Dave Cochran, but if you ever owned a scientific calculator, you owe him, big time. Cochran was “Mr. Algorithm” at Hewlett-Packard starting with the earliest days of HP’s desktop scientific calculators in the late 1960s. He developed the arithmetic and trigonometric algorithms for HP’s first calculator, the HP 9100A … Read More → "In Memoriam: Dave Cochran, an Engineer’s Engineer"
Meet UVVM: The World’s #1 VHDL Verification Methodology
I’m happy (albeit puzzled) to tell you that things seem to be getting better with respect to verifying FPGA, ASIC, and system-on-chip (SoC) designs. The reason I say this is that the last time I turned my attention to this arena, people were saying that the design and verification phases of a complex device consumed 30% and 70% of the total development time, respectively. By comparison, someone recently … Read More → "Meet UVVM: The World’s #1 VHDL Verification Methodology"



