The upshot: Memories can be arranged such that an “access” becomes a multiply-accumulate function. Storing weights in the memory and using activations as inputs saves data movement and power. And there are multiple ways to do this using RRAM, flash, and SRAM – and then there’s an approach involving DRAM, but it’s completely different.
In the scramble … Read More → "In-Memory Computing"
In part 1 of this series, we looked at new high-end FPGA families from Xilinx, Intel, and Achronix and discussed their underlying semiconductor processes, the type and amount of programmable logic LUT fabric, the type and amount of DSP/arithmetic resources and their applicability to AI inference acceleration tasks, the claimed TOPS/FLOPS performance capabilities, and on-chip interconnect … Read More → "High-End FPGA Showdown – Part 3"
In Part 1 of this 3-part miniseries, we discussed the origins of artificial intelligence (AI), and we considered some low-hanging AI-enabled fruit in the form of speech recognition, voice control, and machine vision. In Part 2, we noted some of the positive applications of AI, like recognizing skin cancer, identifying the source of … Read More → "The Artificial Intelligence Apocalypse (Part 3)"
In Part 1 of this 3-part miniseries, we cogitated and ruminated on the origins of artificial intelligence (AI). We also started to look at some of the “happy face” aspects of AI in the form of speech recognition, voice control, and machine vision.
Let’s continue with our happy faces for a moment. AI is now turning up in … Read More → "The Artificial Intelligence Apocalypse (Part 2)"
We’re serving up a double helping of field programmable goodness in this week’s episode of Amelia’s Weekly Fish Fry podcast. Dianne Kibbey (element14) and I dish about this year’s Path II Programmable design series. We discuss the details of this innovative program and how you sign up to participate in this FPGA-based program. Also this week, Geoff Tate (CEO – Flex Logix) and I … Read More → "FPGA Fiesta"