EEJournal

fish fry
Subscribe Now
December 17, 2021

The Most Important Compute Workloads of a Generation: How Cerebras Systems is Accelerating AI’s Potential

by Amelia Dalton

It’s a bird, it’s a plane, it’s the largest AI processor ever made!  In this week’s Fish Fry podcast, Andy Hock (Cerebras Systems) joins me to chat about the largest AI processor ever made –  the 7 nm wafer scale engine 2, the details of their brain-scale AI training, and how Cerebras Systems is democratizing access to high performance AI computation. Also this week, I check out a new kickstarter campaign called the SPORTSMATE 5: the world’s first and lightest portable wearable robotic exoskeleton that aims to alter the way we interact with the world by applying exoskeletons to daily life.

 

Click here to download this episode

 

Links for December 17, 2021

More information about Cerebras Systems

Kickstarter Corner: SPORTSMATE 5: the world’s first and lightest portable wearable robotic exoskeleton

 

 

Click here to check out the Fish Fry Archive.

Click here to subscribe to Fish Fry via Podbean

Click here to get the Fish Fry RSS Feed

Click here to subscribe to Fish Fry via Apple Podcasts

Click here to subscribe to Fish Fry via Spotify

 

Fish Fry Executive Interviews

Anupam Bakshi, CEO – Agnisys

Dave Kleidermacher, CTO – Green Hills Software

Robert Blake, CEO – Achronix

Jack Harding, CEO – eSilicon

Michiel Ligthart, COO – Verific

Adnan Hamid, CEO – Breker Technologies

Simon Davidmann, CEO – Imperas

Jessica Gomez – Rogue Valley Microdevices

Shishpal Rawat, Chairman – Accellera Systems Initiative

Kevin Bromber, CEO – myDevices

Daniel Hansson, CEO – Verifyter

Mark Papermaster, CTO – AMD

David Fried, CTO – Coventor

Dr. Steven LeBoeuf, President – Valencell

David Dutton, CEO – Silvaco

Bob Niemiec, CEO – TwistThink

Allan Martinson, COO – Starship Technologies

Zhihong Liu, Chairman and CEO – ProPlus Solutions

Taher Madraswala, CEO and President – Open-Silicon

Kapil Shankar, CEO and Director – AnDAPT

Dan Fox, CTO – Local Motors

Kim Rowe, Founder and CEO — RoweBots

Lawrence Cooke, Founder and CEO — NovaSolix

Gregg Recupero, CTO — Performance-IP

Alan Grau, CEO — Icon Labs

Carl Alberty, Vice President – Cirrus Logic

Maximilian Odendahl, CEO — Silexica

Finbarr Moynihan, General Manager — MediaTek

Sanjay Pillay, CEO — Austemper

Louis Parks, CEO – SecureRF

Harold Blomquist, CEO – Helix Semiconductor

Dale Dougherty and Sherry Huss, Co-Founders – Maker Faire

Mike Wisart, CEO – efabless

Chris Giovanniello, SVP and Co-Founder – Menlo Micro

Jake Janovetz, President – Opal Kelly

Jerry Gipper, Executive Director – VITA

Ethan Plotkin, CEO – GDCA

Xin Song, CEO – Bottos

Chris Dries, CEO – UnitedSiC 

Bob Smith, Executive Director – ESD Alliance 

Rick O’Connor, Executive Director – RISC V Foundation

Naveed Sherwani, CEO and Yunsup Lee, CTO/Founder- SiFIve

Doug Letcher, CEO and President – Metrics Technologies

Jun Pei, CEO – Cepton Technologies

Nikos Zervas, CEO – CAST

Dave Hughes, CEO – HCC Embedded

David Su, CEO – Atomic Technologies

Jess Isquith, President/CEO – PICMG

Galen Hunt, Distinguished Engineer and Managing Director, Microsoft Azure Sphere – Microsoft 

Vinay Gokhale, VP Business Development – ThirdWayv

Kevin Hannah, Director of Product Operations- Kazuhm

Srinath Anantharaman, CEO – ClioSoft

Gajinder Panesar, CTO  – UltraSoC and Tim Ramsdale, CEO – Agile Analog

Steve Cammish, VP of Edge Solutions – ADLINK

Adam Benzion, Co-Founder, Hackster.io

Ted Pawela, COO – Altium 

Michael Dick, CEO – C2A Security

Ted Mirracco, CEO – Cylynt 

Arun Subbarao, VP of Engineering – Lynx Software

Doug Sandy, Chief Technical Officer – PICMG

Stefan Müller, CTO and Founder – FMC

Brian Faith, CEO – QuickLogic 

Paul Cunningham, Senior Vice President and General Manager- Cadence Design Systems

Tom Doyle, CEO – Aspinity

Pim Tulys, CEO – Intrinsic-ID

Yonatan Geifman , Co-founder and CEO – Deci

Mung Chiang, EVP and Dean of Engineering College – Purdue University

Clay Johnson, CEO – CacheQ

Leave a Reply

featured blogs
Training Insights – Want to Learn How to Test the Design and Its Need?
Dec 1, 2023
Why is Design for Testability (DFT) crucial for VLSI (Very Large Scale Integration) design? Keeping testability in mind when developing a chip makes it simpler to find structural flaws in the chip and make necessary design corrections before the product is shipped to users. T...
More from Cadence...
Meet Synopsys.ai Copilot, Industry's First GenAI Capability for Chip Design
Nov 27, 2023
See how we're harnessing generative AI throughout our suite of EDA tools with Synopsys.AI Copilot, the world's first GenAI capability for chip design.The post Meet Synopsys.ai Copilot, Industry's First GenAI Capability for Chip Design appeared first on Chip Design....
More from Synopsys...
A Haunting World Underwater
Nov 6, 2023
Suffice it to say that everyone and everything in these images was shot in-camera underwater, and that the results truly are haunting....
More from Max's Cool Beans...

featured video

Dramatically Improve PPA and Productivity with Generative AI

Sponsored by Cadence Design Systems

Discover how you can quickly optimize flows for many blocks concurrently and use that knowledge for your next design. The Cadence Cerebrus Intelligent Chip Explorer is a revolutionary, AI-driven, automated approach to chip design flow optimization. Block engineers specify the design goals, and generative AI features within Cadence Cerebrus Explorer will intelligently optimize the design to meet the power, performance, and area (PPA) goals in a completely automated way.

Click here for more information

featured paper

3D-IC Design Challenges and Requirements

Sponsored by Cadence Design Systems

While there is great interest in 3D-IC technology, it is still in its early phases. Standard definitions are lacking, the supply chain ecosystem is in flux, and design, analysis, verification, and test challenges need to be resolved. Read this paper to learn about design challenges, ecosystem requirements, and needed solutions. While various types of multi-die packages have been available for many years, this paper focuses on 3D integration and packaging of multiple stacked dies.

Click to read more

featured chalk talk

Littelfuse Protection IC (eFuse)
Sponsored by Mouser Electronics and Littelfuse
If you are working on an industrial, consumer, or telecom design, protection ICs can offer a variety of valuable benefits including reverse current protection, over temperature protection, short circuit protection, and a whole lot more. In this episode of Chalk Talk, Amelia Dalton and Pete Pytlik from Littelfuse explore the key features of protection ICs, how protection ICs compare to conventional discrete component solutions, and how you can take advantage of Littelfuse protection ICs in your next design.
Click here for more information about Littelfuse Protection eFuse ICs
May 8, 2023
26,815 views