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The Old Man and the C Debugger

“Eliminate all other factors, and the one which remains must be the truth.” – Sherlock Holmes, The Sign of Four

Three engineers are sitting in a rowboat. None of them has any nautical experience or navigational instruments.

As hope for rescue fades, and with no other ships in sight, they pass the time discussing their careers (as … Read More → "The Old Man and the C Debugger"

Security from the Ground Up

It takes 8,460 bolts to assemble an automobile, and one nut to scatter it all over the road.  – Author Unknown

Hello, my name is Amelia and I have read at least four hundred press releases about automotive design this week. It seems that this year’s Consumer Electronics Show has been taken over by automotive design. But behind the pomp and sparkle of CES lies the … Read More → "Security from the Ground Up"

When Safety is King, NAND Reigns Supreme

In this week’s episode of Fish Fry, we investigate the changing role of NAND flash in safety-based systems. Dave Hughes (CEO – HCC Embedded) joins us to discuss HCC’s “Safety Element out of Context” embedded software approach and how HCC helping engineers better use NAND flash in safety systems. Also this week, we give everyone another chance to win a “Hitchhiker’s Guide … Read More → "When Safety is King, NAND Reigns Supreme"

Ye Olde FPGA Acceleration

Unless you’ve been hiding under a rock, you know that FPGA-based compute acceleration is suddenly a hot topic. And, even from under the rock, you probably got the memo that Intel paid over $16B to acquire Altera a couple years back – mostly to capitalize on this “new” emerging killer app for FPGA technology. These days there is an enormous battle brewing for control … Read More → "Ye Olde FPGA Acceleration"

Xilinx Scores Azure Acceleration Win

Xilinx scored a major win recently, with Microsoft’s Azure cloud group reportedly making a commitment to use Xilinx devices in something like half of their future Azure deployments. Until now, Azure has been solidly in the Intel PSG (Altera) camp for FPGA-based acceleration. Microsoft says that every Azure server for the past several years has been equipped with FPGAs, and, until now, those … Read More → "Xilinx Scores Azure Acceleration Win"

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featured blogs
Feb 17, 2019
https://youtu.be/ZuoAfBXsbGw Made in front of the green screen (camera Sean) Monday: SPIE 2019: Light Entertainment Tuesday: DVCon Preview: The Year of PSS Wednesday: MWC Barcelona: 5G in Catalonia... [[ Click on the title to access the full blog on the Cadence Community sit...
Feb 15, 2019
This year at DVCon US, Mentor is going to add some sizzle to our booth (#1005) during the exhibit hours. In addition to our stellar demo staff who are always available to answer questions and show you the latest capabilities of our tools, we’re also going to be hosting ...
Feb 14, 2019
Samtec'€™s complete line of discrete wire connectors and cable assemblies are used in a variety of applications, including industrial automation, industrial equipment, security, telecom, automation, controls, military and defense, and transportation, to name a few. Samtec d...
Jan 25, 2019
Let'€™s face it: We'€™re addicted to SRAM. It'€™s big, it'€™s power-hungry, but it'€™s fast. And no matter how much we complain about it, we still use it. Because we don'€™t have anything better in the mainstream yet. We'€™ve looked at attempts to improve conven...
chalk talks
Introducing Cadence Cloud Portfolio  EDA in the cloud has finally arrived! Now, when you need access to large amounts of computing power to push your design through those critical stages, there is a secure, reliable, powerful cloud-based system that lets you scale your design tools to meet your actual needs. In this episode of Chalk Talk, Amelia Dalton … Read More → "Introducing Cadence Cloud Portfolio"
Introducing the Visual Verification Suite’s New HDL Creator  Finding errors in a complex HDL design can be a daunting task. And, most errors aren’t detected until late in the design flow. If we could catch our errors earlier, when we are initially writing the code, we could save enormous amounts of time in simulation, synthesis, and layout. In this episode of Chalk … Read More → "Introducing the Visual Verification Suite’s New HDL Creator"
Shift Left for Fewer PCB Re-Spins   Design rule checking (DRC) is becoming more important with today’s complex PCB designs. With the complexity of today’s designs, the old ad-hoc methods just don’t cut it. In this episode of Chalk Talk, Amelia Dalton chats with Rory Riggs from Mentor about how Hyperlynx DRC can help get your next design out on … Read More → "Shift Left for Fewer PCB Re-Spins"
Renesas Synergy™ Platform – Mouser and Renesas IoT product development can have a lot of hidden costs and schedule traps. To get your project done on time and on budget, you really need a centralized development environment that can bring the design flow under control. In this episode of Chalk Talk, Amelia Dalton chats with Henrik Flodell of Renesas about how … Read More → "Renesas Synergy™ Platform – Mouser and Renesas"
GUI Made Easy: Modernize Your Embedded Application in Minutes – Mouser and NXPIs your embedded application struggling with a 1990s user interface? It doesn’t have to be. Developing a clean, attractive, modern user interfaces can be easy if you have the right tools. In this episode of Chalk Talk, Amelia Dalton chats with Brendon Slade of NXP about how to modernize your embedded application GUI – in … Read More → "GUI Made Easy: Modernize Your Embedded Application in Minutes – Mouser and NXP"
Simulating Systems with PSpiceSimple simulation just doesn't cut it with today's complex board designs. To manage the tradeoff between accuracy and performance, you need a variety of models with multiple levels of abstraction. In this episode of Chalk Talk, Amelia Dalton chats with Parag Choudhary of Cadence Design Systems about simulating with PSpice.