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Inside Intel Agilex FPGAs

One of the most interesting announcements in Intel’s tidal wave of “Data-Centric” product and technology rollouts this month was the introduction of the company’s new “Agilex” FPGA families – formerly code-named “Falcon Mesa.” Agilex is the first new FPGA line developed by the former Altera group (now Intel PSG) since the Intel acquisition. Agilex is a milestone in the evolution of FPGA technology, and it … Read More → "Inside Intel Agilex FPGAs"

Intel Rolls New Xeon Servers and More

Today, Intel made what is likely to be their most important announcement of the year, or perhaps the next couple of years. Clearly the biggest headliner is the introduction of the “Second Generation Xeon Scalable Processors,” which are intended to carry the heaviest load in defending Intel’s estimated 99% market share in data center processors. But the breadth of the announcement is staggering and goes well … Read More → "Intel Rolls New Xeon Servers and More"

More than Just Silicon

In this week’s episode of Fish Fry, we investigate the challenges SoC Design with ClioSoft CEO Srinath Anantharaman. Srinath and I are chat about the hidden advantages of IP management, the challenges of global design teams, and how IP reuse can make all the difference in your bottom line. In this week’s Kickstarter corner, we also take a closer look at the details of a new mind-controlled … Read More → "More than Just Silicon"

The Moon, Moore’s Law, and Marketing

I believe that this nation should commit itself to achieving the goal, before this decade is out, of landing a man on the moon and returning him safely to the Earth.

– John F Kennedy, May 25, 1961

The complexity for minimum component costs has increased at a rate of roughly a factor of two per year… by 1975, the number of components per integrated circuit … Read More → "The Moon, Moore’s Law, and Marketing"

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featured blogs
Apr 23, 2019
Paul Cunningham was interviewed by Jim Hogan at the latest ESD Alliance "fireside chat". Ever since Lip-Bu's fireside chat at DAC was interrupted by the fire-alarms due to a real fire,... [[ Click on the title to access the full blog on the Cadence Community s...
Apr 22, 2019
I am honored to have the opportunity to serve as the 2019 DAC Technical Program Chair, and this has been an exceptional year in terms of research and Designer/IP track submitted content. The Design Automation Conference (DAC) was founded in 1964 and is the longest running an...
Apr 18, 2019
Thermal Shock testing isn’t unique to the connector world, but it does play a big role in the qualification testing that Samtec puts all connectors through before they are released for production. Chances are likely that you thermally shock many items per day and don...
Jan 25, 2019
Let'€™s face it: We'€™re addicted to SRAM. It'€™s big, it'€™s power-hungry, but it'€™s fast. And no matter how much we complain about it, we still use it. Because we don'€™t have anything better in the mainstream yet. We'€™ve looked at attempts to improve conven...
chalk talks
Tensilica HiFi DSP   Performing speech recognition at the edge, rather than sending data back to the cloud, is a major engineering challenge. You need significant processing power on a tiny energy budget, and often in a small form-factor. In this episode of Chalk Talk, Amelia Dalton chats with Gerard Andrews of Cadence Design Systems about the … Read More → "Tensilica HiFi DSP"
Overcoming Today’s RFIC and SiP Design Challenges with Virtuoso RF Solution   5G presents daunting challenges for RF design. RF modules are reaching a level of complexity such that verification and analysis now demand about half of the design time, and that requires an integrated flow including physical verification and analysis as well as circuit design. In this episode of Chalk Talk, Amelia Dalton chats … Read More → "Overcoming Today’s RFIC and SiP Design Challenges with Virtuoso RF Solution"
Introducing Cadence Cloud Portfolio  EDA in the cloud has finally arrived! Now, when you need access to large amounts of computing power to push your design through those critical stages, there is a secure, reliable, powerful cloud-based system that lets you scale your design tools to meet your actual needs. In this episode of Chalk Talk, Amelia Dalton … Read More → "Introducing Cadence Cloud Portfolio"
What is Intel® Optane™ Technology? — Mouser Electronics and Intel  Memory architecture is often the biggest bottleneck in a high-performance system design. The gap between high-speed DRAM and higher-capacity non-volatile memory sits at an inconvenient place on the cost-performance curve. In this episode of Chalk Talk, Amelia Dalton chats with Jeffrey Galinovsky of Intel about how new Intel technologies including Intel® Optane™ memory technology … Read More → "What is Intel® Optane™ Technology? — Mouser Electronics and Intel"
A New Advanced IC Packaging Battlefield  Today, advanced packaging technology has created a new battleground where 2.5D packaging and heterogeneous design drive constraints that span semiconductor, packaging, board, and even system-level design. In this episode of Chalk Talk, Amelia Dalton chats with John Park of Cadence Design Systems about new techniques and tools for advanced IC packaging design. Click here … Read More → "A New Advanced IC Packaging Battlefield"
Designing High-Reliability Analog and Mixed-Signal ICs for Mission-Critical Applications  Designing products for reliability and longevity requires a different mindset – and a different tool set from the more common “just get it out the door” engineering methodology. We need to focus on all phases of product life, and do a diligent analysis of the mechanisms that can lead to premature failure in the … Read More → "Designing High-Reliability Analog and Mixed-Signal ICs for Mission-Critical Applications"