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Silicon Carbide’s Time to Shine

We’re running the gamut of electronic design in this week’s episode of Fish Fry. Chris Dries (CEO – UnitedSiC) and I discuss some common cascode issues facing hardware designers today and what UnitedSiC is doing to help ease the pain of those issues. We also chat about the advantages (and limitations) of silicon carbide and why he thinks silicon carbide will become the semiconductor of choice for power … Read More → "Silicon Carbide’s Time to Shine"

Seeing and Being Seen

Vision in living beings is a pretty incredible thing. The eyeball hardware and the brain software seem effortlessly to do what we struggle to do in inorganic hardware and software. But we’re making progress. And, today, we take on two vision topics – but, unlike in the past, they’re not closely related. They’re about two very different aspects of vision. And we’ll take them in the … Read More → "Seeing and Being Seen"

Molto Legato Senza Failure

In music, Legato means smooth and connected, without distinct breaks. Or, in electronics parlance – analog. Analog circuits are arguably the most difficult to design and the most complex to simulate. Engineers with mystical knowledge and decades of experience toil endlessly to find just the right combination of component values that will yield the desired results. And that’s just for the nominal case.

Now, try putting that … Read More → "Molto Legato Senza Failure"

Mid-Range Mayhem

We give far too much air time to high end FPGAs. It’s too easy, really. Our eyes glaze over at all the talk of FinFETs, 58 gig PAM4 SerDes, optical transceivers, HBM stacks, and gazillions of monster-truck LUTs, and we find ourselves hammering away at our keyboards fantasizing about all the amazing things that will be accomplished by these milestone achievements in semiconductor engineering.

< … Read More → "Mid-Range Mayhem"
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featured blogs
May 18, 2018
https://youtu.be/O1r7cqyVm90 I was on China24 on CGTNAmerica earlier this week, being interviewed about the Chinese Semiconductor Industry. www.breakfastbytes.com Sign up for Sunday Brunch, the weekly Breakfast Bytes email....
May 17, 2018
Just about everybody wishes they had more time to pursue a hobby or a side project.  Some aspire to be painters or furniture makers.  Others like to rebuild cars.  Even others enjoy electronics in any form. The Maker Movement attracts and caters to tinkerers, hobbyists, st...
chalk talks
Mixed-Signal Digital Complexity Explosion   Mixed-signal design is becoming increasingly complex, and our old tools and methods just won’t cut it. In this episode of Chalk Talk, Amelia Dalton chats with Rod Metcalfe of Cadence Design Systems about the changing mixed-signal landscape and how Cadence’s robust suite of mixed-signal design solutions can solve your toughest problems. Click here … Read More → "Mixed-Signal Digital Complexity Explosion"
Moving Between FPGA and ASIC with High-Level Synthesis Writing RTL that works smoothly on both FPGA and ASIC implementations is nearly impossible. But, High-Level Synthesis (HLS) can make technology-independent design a breeze. In this episode of Chalk Talk, Amelia Dalton chats with Stuart Clubb of Mentor’s Catapult team about how to use HLS to accelerate your design flow. Click here for more … Read More → "Moving Between FPGA and ASIC with High-Level Synthesis"
Scaling Embedded Deep Learning Inference Performance with Dedicated Neural Network DSP   Neural networks are taking over a broad range of exciting applications these days. But, the amount of computation required for neural network inferencing can be daunting. In this episode of Chalk Talk, Amelia Dalton chats with Pulin Desai of Cadence Design Systems about some new processor IP designed specifically for neural network inferencing. … Read More → "Scaling Embedded Deep Learning Inference Performance with Dedicated Neural Network DSP"
Cadence Xcelium Parallel Simulator: Third Generation Parallel VerificationGetting the best RTL simulation performance is a combination of improving single-core speed and cleverly partitioning the task so that parallel machines can give you the kind of performance boost you’d expect. In this episode of Chalk Talk, Amelia Dalton chats with Dave Lidrbauch from Cadence Design Systems about Xcelium – Cadence’s third-generation parallel RTL simulation … Read More → "Cadence Xcelium Parallel Simulator: Third Generation Parallel Verification"
Pegasus Verification System: Let Your DRC Fly!Design rule checking (DRC) can be the one of the biggest bottlenecks in getting a chip out the door. The computation power required for a large DRC run can be staggering. In this episode of Chalk Talk, Amelia Dalton chats with Christen Decoin from Cadence Design Systems about the Pegasus Verification System which will let your … Read More → "Pegasus Verification System: Let Your DRC Fly!"
JasperGold RTL Designer Signoff with Superlint and CDCRTL signoff is becoming the preferred design methodology for many teams today. But, verifying that your RTL will give you back the chip you want – the first time – is a challenging task. In this episode of Chalk Talk, Amelia Dalton chats with Pete Hardee of Cadence Design Systems about JasperGold, a comprehensive solution … Read More → "JasperGold RTL Designer Signoff with Superlint and CDC"