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Intel Acquires eASIC – Why?

Intel announced last week that they are acquiring structured ASIC company eASIC into their Programmable Systems Group (PSG). If you haven’t been following along in your major merger primer, Intel PSG was formerly known as Altera – one of the two major players in the FPGA market. Altera has played second fiddle to Xilinx in the Duopoly Symphony for the past twenty seasons or so. This … Read More → "Intel Acquires eASIC – Why?"

Long Live the (8 Bit) King

There are whispers that their time has come to fade away into the sunset. Time to drift away on the electronic wind with laser discs, Zune players, and VHS. But can the role of 8 bit MCUs in the electronic engineering ecosystem be dismissed so easily? Maybe not. In this week’s episode of Fish Fry, Nikos Zervas (CEO … Read More → "Long Live the (8 Bit) King"

Is AI the Killer FPGA Application?

Ross Freeman, co-founder of Xilinx, invented the FPGA in 1984. In the 34 years that have passed, FPGAs have been wildly successful and are certainly among the most important electronic devices ever conceived. But during that entire history, tracing the evolution of FPGAs from dozens of LUTs to millions, the FPGA has been the optimal solution for … exactly zero applications.

Don’t get me wrong. FPGAs do one thing … Read More → "Is AI the Killer FPGA Application?"

What (Invisible) Dreams May Come

This week’s episode of Fish Fry, we take a closer look at two childhood dreams of mine: an invisibility cloak and robots that can think! (ie. artificial intelligence.) First up, we examine why an invisibility cloak is closer to reality than ever before, the physics behind invisibility/cloaking, and important differences between three new cloaking technologies. Also this week, I sit down with Carlos Macian from eSilicon and … Read More → "What (Invisible) Dreams May Come"

Xilinx Hits the Road with Daimler

In what appears to be another win for Xilinx’s formidable Zynq SoC FPGA platform, Xilinx and Daimler announced a collaboration on “an in-car system using Xilinx technology for artificial intelligence (AI) processing in automotive applications.” We say this “appears” to be a win for Zynq because Zynq isn’t mentioned by name in the very-vague press release. It does say, however, that the … Read More → "Xilinx Hits the Road with Daimler"

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featured blogs
Jul 20, 2018
https://youtu.be/KwrfcMtbMDM Coming from CDNLive Japan (camera Asushi Tanaka) Monday: Nicolas's Recipe for Digital Marketing in EDA Tuesday: Embargoed announcement Wednesday: Trends, Technologies, and Regulation in China's Auto Market Thursday: Breakfast Bytes Guide...
Jul 19, 2018
In the footer of Samtec.com, we'€™ve always made it easy to contact us by phone, email, or live chat (even fax back in the day!). To continue to progress this theme, you'€™ll now find a new helpful tool in the footer area of Samtec.com. This tool will match you up with yo...
Jul 16, 2018
Each instance of an Achronix Speedcore eFPGA in your ASIC or SoC design must be configured after the system powers up because Speedcore eFPGAs employ nonvolatile SRAM technology to store the eFPGA'€™s configuration bits. Each Speedcore instance contains its own FPGA configu...
Jul 12, 2018
A single failure of a machine due to heat can bring down an entire assembly line to halt. At the printed circuit board level, we designers need to provide the most robust solutions to keep the wheels...
chalk talks
Scaling Up Vision and AI DSP Performance  For high-performance, low-power processing of AI and machine vision algorithms, latency can be critical. In this episode of Chalk Talk, Amelia Dalton chats with Pulin Desai from Cadence Design Systems about the using the new Vision Q6 processor core for embedded vision and AI applications. Click here for more information about Vision DSPs for … Read More → "Scaling Up Vision and AI DSP Performance"
Debug and Verify FPGA Algorithms with MATLAB and Simulink   Today’s FPGA designs require industrial-strength functional verification. The ad-hoc methods that worked with older, smaller FPGAs just don’t cut it anymore. In this episode of Chalk Talk, Amelia Dalton chats with Eric Cigan of MathWorks about ASIC-strength functional verification with model-based design. Click here for more information about how to verify VHDL and … Read More → "Debug and Verify FPGA Algorithms with MATLAB and Simulink"
Mixed-Signal Digital Complexity Explosion   Mixed-signal design is becoming increasingly complex, and our old tools and methods just won’t cut it. In this episode of Chalk Talk, Amelia Dalton chats with Rod Metcalfe of Cadence Design Systems about the changing mixed-signal landscape and how Cadence’s robust suite of mixed-signal design solutions can solve your toughest problems. Click here … Read More → "Mixed-Signal Digital Complexity Explosion"
Moving Between FPGA and ASIC with High-Level Synthesis Writing RTL that works smoothly on both FPGA and ASIC implementations is nearly impossible. But, High-Level Synthesis (HLS) can make technology-independent design a breeze. In this episode of Chalk Talk, Amelia Dalton chats with Stuart Clubb of Mentor’s Catapult team about how to use HLS to accelerate your design flow. Click here for more … Read More → "Moving Between FPGA and ASIC with High-Level Synthesis"
Scaling Embedded Deep Learning Inference Performance with Dedicated Neural Network DSP   Neural networks are taking over a broad range of exciting applications these days. But, the amount of computation required for neural network inferencing can be daunting. In this episode of Chalk Talk, Amelia Dalton chats with Pulin Desai of Cadence Design Systems about some new processor IP designed specifically for neural network inferencing. … Read More → "Scaling Embedded Deep Learning Inference Performance with Dedicated Neural Network DSP"
Cadence Xcelium Parallel Simulator: Third Generation Parallel VerificationGetting the best RTL simulation performance is a combination of improving single-core speed and cleverly partitioning the task so that parallel machines can give you the kind of performance boost you’d expect. In this episode of Chalk Talk, Amelia Dalton chats with Dave Lidrbauch from Cadence Design Systems about Xcelium – Cadence’s third-generation parallel RTL simulation … Read More → "Cadence Xcelium Parallel Simulator: Third Generation Parallel Verification"