Semiconductor
Subscribe Now

The First Emulators of Spring

It’s the season of rebirth. The sun is out. Flowers are in bloom. Birds busily build nests while semiconductor verification teams emerge from their long winter hibernation, ready to tool up for the challenges of the next process generation. Billions of unverified gates give shelter to countless bugs awaiting anxious design teams as they prepare for summer’s tape-outs and struggle to bring new software … Read More → "The First Emulators of Spring"

ARMv9: Fashionably Late

Silicon Valley is like Milan. One is the US center of high tech, the other is the fashion capital of Italy. The Valley has its product rollouts and Milan has its runway shows. Both are glamorous, slick, professionally produced events designed to generate excitement but tell you almost nothing about the actual product. They’re teases; entertainment for the press corps documenting the industry’s every … Read More → "ARMv9: Fashionably Late"

Looking Beyond to Today: Finding New Material Solutions with Intermolecular

What do new material synthesizing, device innovation, and lab-grown organs have in common? This week’s Fish Fry podcast of course! My guest is Casper van Oosten, (Business Field Head and Managing Director at Intermolecular, Inc., a subsidiary of Merck KGaA, Darmstadt, Germany). Casper and I are talking all about synthesizing new materials for … Read More → "Looking Beyond to Today: Finding New Material Solutions with Intermolecular"

A PUF by Any Other Name Just Isn’t the Same

My distinguished guest in this week’s Fish Fry podcast is Intrinsic-ID CEO Pim Tulys. Pim and I discuss the role of hardware-based security in today’s EE ecosystem, where physical unclonable functions are headed in the future, and what Intrinsic ID’s PUF Cafe is all about. Also this week, we take a closer look at the details of a new experiment that might finally bridge the gap … Read More → "A PUF by Any Other Name Just Isn’t the Same"

April 19, 2021
April 15, 2021
April 13, 2021
April 9, 2021
April 6, 2021
April 5, 2021
March 30, 2021
March 29, 2021
March 25, 2021
March 24, 2021
March 23, 2021
March 17, 2021
March 16, 2021
March 12, 2021
March 11, 2021
featured blogs
Apr 19, 2021
Cache coherency is not a new concept. Coherent architectures have existed for many generations of CPU and Interconnect designs. Verifying adherence to coherency rules in SoCs has always been one of... [[ Click on the title to access the full blog on the Cadence Community sit...
Apr 19, 2021
Samtec blog readers are used to hearing about high-performance design. However, we see an increase in intertest in power integrity (PI). PI grows more crucial with each design iteration, yet many engineers are just starting to understand PI. That raises an interesting questio...
Apr 15, 2021
Explore the history of FPGA prototyping in the SoC design/verification process and learn about HAPS-100, a new prototyping system for complex AI & HPC SoCs. The post Scaling FPGA-Based Prototyping to Meet Verification Demands of Complex SoCs appeared first on From Silic...
Apr 14, 2021
By Simon Favre If you're not using critical area analysis and design for manufacturing to… The post DFM: Still a really good thing to do! appeared first on Design with Calibre....
chalk talks
In-Chip Sensing and PVT Monitoring — Synopsys  In-chip monitoring can significantly alter the lifecycle management landscape. By taking advantage of modern techniques, today’s more complex designs can be optimized even after they are deployed. In this episode of Chalk Talk, Amelia Dalton chats with Stephen Crosher of Synopsys about silicon lifecycle management and how to take full advantage of the optimization … Read More → "In-Chip Sensing and PVT Monitoring — Synopsys"
Silicon Lifecycle Management (SLM) — Synopsys  Wouldn’t it be great if we could keep on analyzing our IC designs once they are in the field? After all, simulation and lab measurements can never tell the whole story of how devices will behave in real-world use. In this episode of Chalk Talk, Amelia Dalton chats with Randy Fish of Synopsys about … Read More → "Silicon Lifecycle Management (SLM) — Synopsys"
Accelerating Physical Verification Productivity Part Two — Synopsys  Physical verification of IC designs at today’s advanced process nodes requires an immense amount of processing power. But, getting your design and verification tools to take full advantage of the compute resources available can be a challenge. In this episode of Chalk Talk, Amelia Dalton chats with Manoz Palaparthi of Synopsys about dramatically improving … Read More → "Accelerating Physical Verification Productivity Part Two — Synopsys"
Cloud Computing for Electronic Design (Are We There Yet?)   When your project is at crunch time, a shortage of server capacity can bring your schedule to a crawl. But, the rest of the year, having a bunch of extra servers sitting around idle can be extremely expensive. Cloud-based EDA lets you have exactly the compute resources you need, when you need them. … Read More → "Cloud Computing for Electronic Design (Are We There Yet?)"
SLX FPGA: Accelerate the Journey from C/C++ to FPGA   High-level synthesis (HLS) brings incredible power to FPGA design. But harnessing the full power of HLS with FPGAs can be difficult even for the most experienced engineering teams. In this episode of Chalk Talk, Amelia Dalton chats with Jordon Inkeles of Silexica about using the SLX FPGA tool to truly harness the power … Read More → "SLX FPGA: Accelerate the Journey from C/C++ to FPGA"
TensorFlow to RTL with High-Level Synthesis — Cadence Design Systems   Bridging the gap from the AI and data science world to the RTL and hardware design world can be challenging. High-level synthesis (HLS) can provide a mechanism to get from AI frameworks like TensorFlow into synthesizable RTL, enabling the development of high-performance inference architectures. In this episode of Chalk Talk, Amelia Dalton chats … Read More → "TensorFlow to RTL with High-Level Synthesis — Cadence Design Systems"