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Who Chooses Components and Tools?

Before becoming professional engineers, most of us designed and built things as a hobby. It’s rare to find an engineer who jumped right into engineering school without at least some background of tinkering and experimenting. And, when we did those projects, we had full control. We could choose whatever part we wanted or needed. We didn’t have to deal with management, manufacturing, … Read More → "Who Chooses Components and Tools?"

Achronix Accelerates eFPGA

Perhaps when the most important problem is a nail, every solution starts to look like a hammer. With the ramping explosion in AI and machine learning, countless companies are trying to climb on the bandwagon, morphing and melding their existing technologies in an attempt to come up with a differentiated solution that will capture a meaningful share of this mind-boggling emerging opportunity. Everybody from EDA vendors to cloud data … Read More → "Achronix Accelerates eFPGA"

The Spirit of 42

What do Douglas Adams, PCB design, DRAM for cryptocurrency, and the fourth Industrial Revolution have in common? This week’s episode of Amelia’s Weekly Fish Fry, of course! First up, Greg Roberts (EMA Design Automation) brings us the goods on EMA’s new ebook called “The Hitchhiker’s Guide to PCB Design”. Next, Mark Greenberg (Cadence Design Systems) and I chat about using DRAM4 for artificial … Read More → "The Spirit of 42"

What Will Replace DRAM and NAND, and When?

Long, long ago, back when Richard Nixon was president of the United States of America, magnetic cores were the dominant computer memory technology. In fact, magnetic cores were essentially the only practical memory technology for two decades. Although we had hand-woven rope memory for ROM, only the Apollo space computers and the HP 9100 desktop calculator used it. My 1954 “Britannica Book of the Year”—a real book, … Read More → "What Will Replace DRAM and NAND, and When?"

Racing to the End of Moore’s Law: The New World Semiconductor Order

There’s a new world order coming for the semiconductor industry, said A.B. Kahng. We’re racing to the end of Moore’s Law, and the race will now be won by sheer capex (capital expenditures) and size. Kahng, Professor of CSE and ECE at UC San Diego, was speaking at the < … Read More → "Racing to the End of Moore’s Law: The New World Semiconductor Order"

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featured blogs
Dec 11, 2018
Over the past few years, Samtec has expanded its portfolio of Characterization and Development Kits. Engineers and designer demand the best tools for system prototyping. From concept and prototype to development and production, Samtec-designed Characterization and Development...
Dec 11, 2018
The first week of December means it is IEDM, the International Electron Devices Meeting. This meeting pre-dates the integrated circuit and nearly pre-dates the transistor, so "electron... [[ Click on the title to access the full blog on the Cadence Community site. ]]...
Dec 10, 2018
We may think of prosthetics as devices created to enable basic functions, such as walking or grasping an object. Regarded as a necessity, but not an asset, prosthetics of the past......
Nov 14, 2018
  People of a certain age, who mindfully lived through the early microcomputer revolution during the first half of the 1970s, know about Bill Godbout. He was that guy who sent out crudely photocopied parts catalogs for all kinds of electronic components, sold from a Quon...
chalk talks
A New Advanced IC Packaging Battlefield  Today, advanced packaging technology has created a new battleground where 2.5D packaging and heterogeneous design drive constraints that span semiconductor, packaging, board, and even system-level design. In this episode of Chalk Talk, Amelia Dalton chats with John Park of Cadence Design Systems about new techniques and tools for advanced IC packaging design. Click here … Read More → "A New Advanced IC Packaging Battlefield"
Designing High-Reliability Analog and Mixed-Signal ICs for Mission-Critical Applications  Designing products for reliability and longevity requires a different mindset – and a different tool set from the more common “just get it out the door” engineering methodology. We need to focus on all phases of product life, and do a diligent analysis of the mechanisms that can lead to premature failure in the … Read More → "Designing High-Reliability Analog and Mixed-Signal ICs for Mission-Critical Applications"
Scaling Up Vision and AI DSP Performance  For high-performance, low-power processing of AI and machine vision algorithms, latency can be critical. In this episode of Chalk Talk, Amelia Dalton chats with Pulin Desai from Cadence Design Systems about the using the new Vision Q6 processor core for embedded vision and AI applications. Click here for more information about Vision DSPs for … Read More → "Scaling Up Vision and AI DSP Performance"
Debug and Verify FPGA Algorithms with MATLAB and Simulink   Today’s FPGA designs require industrial-strength functional verification. The ad-hoc methods that worked with older, smaller FPGAs just don’t cut it anymore. In this episode of Chalk Talk, Amelia Dalton chats with Eric Cigan of MathWorks about ASIC-strength functional verification with model-based design. Click here for more information about how to verify VHDL and … Read More → "Debug and Verify FPGA Algorithms with MATLAB and Simulink"
Mixed-Signal Digital Complexity Explosion   Mixed-signal design is becoming increasingly complex, and our old tools and methods just won’t cut it. In this episode of Chalk Talk, Amelia Dalton chats with Rod Metcalfe of Cadence Design Systems about the changing mixed-signal landscape and how Cadence’s robust suite of mixed-signal design solutions can solve your toughest problems. Click here … Read More → "Mixed-Signal Digital Complexity Explosion"
Moving Between FPGA and ASIC with High-Level Synthesis Writing RTL that works smoothly on both FPGA and ASIC implementations is nearly impossible. But, High-Level Synthesis (HLS) can make technology-independent design a breeze. In this episode of Chalk Talk, Amelia Dalton chats with Stuart Clubb of Mentor’s Catapult team about how to use HLS to accelerate your design flow. Click here for more … Read More → "Moving Between FPGA and ASIC with High-Level Synthesis"