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Moore’s Law Only Ends Once

I hope you have your seatbelt low and tight across your waist my friends, because we are flying high into cloud-based design in this week’s episode of Fish Fry! With templates, code, tools, fabs and processes in the cloud cargo hold, Naveed Sherwani (CEO – SiFive), Yunsup Lee (CTO/Founder – SiFive), and I are headed straight into the next generation of silicon design. Also this week, … Read More → "Moore’s Law Only Ends Once"

0.6V, and Still the Memory Persisted

A big chunk of the vast, imagined IoT (Internet of Things) includes the industrial IoT (IIoT), which is responsible for controlling and monitoring energy-consuming processes based on large motors, pumps, fans, generators, heavy-duty actuators, heaters, and other high-power equipment. Such IIoT applications aren’t as concerned with low-power design compared to the medical and consumer side of the IoT—wearables and the like. Medical and consumer … Read More → "0.6V, and Still the Memory Persisted"

High Bandwidth, Modest Capacity

Aaaaand… it’s memory time again. I don’t keep up with every release of memory (who could keep up with that without dedicating their lives to nothing but that?), but here and there we have either technology or application angles to new-memory stories. So, in that vein, we address memory in automotive and AI. Yes, two critical keywords in any tech article these days.Read More → "High Bandwidth, Modest Capacity"

Infinitely Parallel

They say that on a clear day you can see forever. When you look into the clouds, do you see System Verilog? In this week’s episode of Fish Fry, you will! Doug Letcher (CEO and President – Metrics Technologies) joins us to chat about details of the Metrics cloud platform, verification 3.0 and why EDA cannot ignore the Cloud any longer. Also this week, we check out a new robotic … Read More → "Infinitely Parallel"

Brainchip Debuts Neuromorphic Chip

Convolutional Neural Networks (CNNs)  have been dominating the discussion on AI advancement for the past couple of years. But CNNs have one glaring weakness – a heavy reliance on massive amounts of multiplication. This huge arithmetic obstacle has led to a plethora of initiatives to accelerate both the training and inference phases of deep learning with CNNs, and a wide variety of hardware and software architectures designed … Read More → "Brainchip Debuts Neuromorphic Chip"

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featured blogs
Sep 21, 2018
在这我们谈论的不是您的叠层设计跟其他人比怎么样,而是您设计的 PCB 层叠结构,是刚性板、柔性板、刚...
Sep 21, 2018
  FPGA luminary David Laws has just published a well-researched blog on the Computer History Museum'€™s Web site titled '€œWho invented the Microprocessor?'€ If you'€™re wildly waving your raised hand right now, going '€œOoo, Ooo, Ooo, Call on me!'€ to get ...
Sep 20, 2018
Last week, NVIDIA announced the release of the Jetson Xavier developer kit. The Jetson Xavier, which was developed in OrCAD, is designed to help developers prototype with robots, drones, and other......
Sep 18, 2018
Samtec performs several tests in-house as part of our qualification testing on a product series; including Low Level Contact Resistance (LLCR). It measures the amount of resistance in a position on a part. LLCR is used in combination with several other tests to track the over...
chalk talks
Scaling Up Vision and AI DSP Performance  For high-performance, low-power processing of AI and machine vision algorithms, latency can be critical. In this episode of Chalk Talk, Amelia Dalton chats with Pulin Desai from Cadence Design Systems about the using the new Vision Q6 processor core for embedded vision and AI applications. Click here for more information about Vision DSPs for … Read More → "Scaling Up Vision and AI DSP Performance"
Debug and Verify FPGA Algorithms with MATLAB and Simulink   Today’s FPGA designs require industrial-strength functional verification. The ad-hoc methods that worked with older, smaller FPGAs just don’t cut it anymore. In this episode of Chalk Talk, Amelia Dalton chats with Eric Cigan of MathWorks about ASIC-strength functional verification with model-based design. Click here for more information about how to verify VHDL and … Read More → "Debug and Verify FPGA Algorithms with MATLAB and Simulink"
Mixed-Signal Digital Complexity Explosion   Mixed-signal design is becoming increasingly complex, and our old tools and methods just won’t cut it. In this episode of Chalk Talk, Amelia Dalton chats with Rod Metcalfe of Cadence Design Systems about the changing mixed-signal landscape and how Cadence’s robust suite of mixed-signal design solutions can solve your toughest problems. Click here … Read More → "Mixed-Signal Digital Complexity Explosion"
Moving Between FPGA and ASIC with High-Level Synthesis Writing RTL that works smoothly on both FPGA and ASIC implementations is nearly impossible. But, High-Level Synthesis (HLS) can make technology-independent design a breeze. In this episode of Chalk Talk, Amelia Dalton chats with Stuart Clubb of Mentor’s Catapult team about how to use HLS to accelerate your design flow. Click here for more … Read More → "Moving Between FPGA and ASIC with High-Level Synthesis"
Scaling Embedded Deep Learning Inference Performance with Dedicated Neural Network DSP   Neural networks are taking over a broad range of exciting applications these days. But, the amount of computation required for neural network inferencing can be daunting. In this episode of Chalk Talk, Amelia Dalton chats with Pulin Desai of Cadence Design Systems about some new processor IP designed specifically for neural network inferencing. … Read More → "Scaling Embedded Deep Learning Inference Performance with Dedicated Neural Network DSP"
Cadence Xcelium Parallel Simulator: Third Generation Parallel VerificationGetting the best RTL simulation performance is a combination of improving single-core speed and cleverly partitioning the task so that parallel machines can give you the kind of performance boost you’d expect. In this episode of Chalk Talk, Amelia Dalton chats with Dave Lidrbauch from Cadence Design Systems about Xcelium – Cadence’s third-generation parallel RTL simulation … Read More → "Cadence Xcelium Parallel Simulator: Third Generation Parallel Verification"