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How Do We Tackle Chip Security?

Security was huge at this summer’s DAC. By that, I don’t mean that you had to get frisked to get in; I mean that it was a hot topic of discussion. It came together at a luncheon hosted by the Accellera standards body, with further depth in a separate discussion with Accellera. The highest-level take-away would be… that we – and you – have a lot … Read More → "How Do We Tackle Chip Security?"

To the Cloud, Alice!

It’s like Manifest Destiny all over again (hopefully without the dark side). There’s an inexorable move to the cloud for computing – and yet all the pieces aren’t in place yet to make it ridiculously easy to get secure cloud connections. So today we discuss three different stories about moving to the cloud. One is EDA-related; the others apply to automotive and the Internet … Read More → "To the Cloud, Alice!"

Seeing is Believing

What has SLAM done for you lately? If you are working on a vision processing application, quite a lot most likely! In this week’s episode of Fish Fry, we welcome Pulin Desai from Cadence Design Systems. Pulin and I chat about the trends driving the need for more vision processing, the current challenges associated with SLAM (simultaneous localization and mapping) and when he thinks it is best to … Read More → "Seeing is Believing"

Swimming in the SoC

In this week’s episode of Fish Fry, we are swimming in SoCs! Randy Fish (UltraSoC) joins us to discuss the deep waters of embedded analytics and AI platform debug. Ramsay Allen (Moortec) and I chat about the rising tide of advanced chip node designs and the benefits of in-chip monitoring IP. Finally, Rob van Blommestein (OneSpin) and sail through the choppy waters of IC verification. </ … Read More → "Swimming in the SoC"

The Coming Disintegration

It’s an idea rooted in the very identity of the products that the semiconductor industry puts out: the integrated circuit (or IC). For decades, our job has been to take lots of things that used to exist as separate components – transistors, resistors, capacitors, and such – and build them all in close proximity on a single monolithic piece of silicon.

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featured blogs
Aug 22, 2019
If you missed the first part of this series, you can find it here . So: what does Green Hills propose we do? The issue of '€œsolving security'€ is, at its core, impossible'€”security can never be 100%... [[ Click on the title to access the full blog on the Cadence Com...
Aug 21, 2019
Many electronics experience a wide range of climates while in operation and storage. Because of this fact, connector humidity testing is used to determine the ability of a product to withstand elevated humidity and cycling temperatures. Humidity testing is conducted in combin...
chalk talks
Accelerating Physical Verification Productivity   Physical verification can take an enormous amount of time, and catching errors early in the process is the best way to avoid costly and time-consuming iterations. In this episode of Chalk Talk, Amelia Dalton chats with Christen Decoin of Synopsys about accelerating physical design productivity with tools and methods that can help catch … Read More → "Accelerating Physical Verification Productivity"
Tensilica HiFi DSP   Performing speech recognition at the edge, rather than sending data back to the cloud, is a major engineering challenge. You need significant processing power on a tiny energy budget, and often in a small form-factor. In this episode of Chalk Talk, Amelia Dalton chats with Gerard Andrews of Cadence Design Systems about the … Read More → "Tensilica HiFi DSP"
Overcoming Today’s RFIC and SiP Design Challenges with Virtuoso RF Solution   5G presents daunting challenges for RF design. RF modules are reaching a level of complexity such that verification and analysis now demand about half of the design time, and that requires an integrated flow including physical verification and analysis as well as circuit design. In this episode of Chalk Talk, Amelia Dalton chats … Read More → "Overcoming Today’s RFIC and SiP Design Challenges with Virtuoso RF Solution"
Introducing Cadence Cloud Portfolio  EDA in the cloud has finally arrived! Now, when you need access to large amounts of computing power to push your design through those critical stages, there is a secure, reliable, powerful cloud-based system that lets you scale your design tools to meet your actual needs. In this episode of Chalk Talk, Amelia Dalton … Read More → "Introducing Cadence Cloud Portfolio"
What is Intel® Optane™ Technology? — Mouser Electronics and Intel  Memory architecture is often the biggest bottleneck in a high-performance system design. The gap between high-speed DRAM and higher-capacity non-volatile memory sits at an inconvenient place on the cost-performance curve. In this episode of Chalk Talk, Amelia Dalton chats with Jeffrey Galinovsky of Intel about how new Intel technologies including Intel® Optane™ memory technology … Read More → "What is Intel® Optane™ Technology? — Mouser Electronics and Intel"
A New Advanced IC Packaging Battlefield  Today, advanced packaging technology has created a new battleground where 2.5D packaging and heterogeneous design drive constraints that span semiconductor, packaging, board, and even system-level design. In this episode of Chalk Talk, Amelia Dalton chats with John Park of Cadence Design Systems about new techniques and tools for advanced IC packaging design. Click here … Read More → "A New Advanced IC Packaging Battlefield"