EEJournal

Semiconductor
Subscribe Now

Silexica Bridges the HLS Gap

The New “Computing” Comes of Age
by Kevin Morris - January 15, 2020

Today, we call it “acceleration” – the use of specialized hardware to optimize compute tasks that do not perform well on conventional von Neumann processors. We have entered an “age of acceleration” driven primarily by the explosion in AI technology. Countless startups are engaged in developing chips with alternative architectures that accelerate and parallelize various types of compute-intensive algorithms. As a result, we are living in a … Read More → "Silexica Bridges the HLS Gap"

Thermal Trials and Temperature Tales

Thermal-Electric Co-Simulation for System Analysis
by Amelia Dalton - January 10, 2020

We all know that today’s engineering teams are facing increasing challenges surrounding thermal aware designs. Whether you are designing a board, an IC, or a system, we all struggle with thermal and electrical simulation at one point or another. In this week’s Fish Fry, Jerry Zhao (Cadence Design Systems) and I discuss the challenges of thermal and electrical simulation and the benefits of electrical and thermal co-simulation … Read More → "Thermal Trials and Temperature Tales"

Hyperscale to the Rescue

To 800G and Beyond
by Amelia Dalton - January 3, 2020

In this week’s podcast we take a closer look at how the increase of machine to machine data traffic has encouraged a movement toward spine leaf architecture and die-to-die connectivity in hyperscale data centers. Manmeet Walia (Synopsys) joins me this week to discuss the evolution of data center technology and how the challenges surrounding cache currency and network functionality is driving change in the world of hyper scale … Read More → "Hyperscale to the Rescue"

Articles Archive →
industry news
January 17, 2020
Microchip Joins Responsible Business Alliance (RBA) – the Global Industry Coalition Dedicated to Corporate Social Responsibility
January 14, 2020
Cadence Expands Collaboration with Broadcom for 5nm and 7nm Designs
December 19, 2019
Aldec Enhances Riviera-PRO’s VHDL and UVVM Support
December 18, 2019
Mobiveil’s PCI Express 4.0 Endpoint Controller Passes PCI-SIG Gold and Interoperability Testing
December 17, 2019
Mentor collaborates with Arm on unique eMRAM test solution using Samsung FDSOI technology
December 13, 2019
Enflame leverages Mentor’s Tessent DFT solutions for innovative cloud AI chip targeting neural network training
December 11, 2019
Lattice Accelerates FPGA Design with New Lattice Radiant 2.0 Design Software
NSITEXE Selects SmartDV TileLink Verification IP for RISC-V Based Applications
December 9, 2019
Imec presents forksheet device as the ultimate solution to push scaling towards the 2nm technology node
December 5, 2019
Keysight, Marvin Test Solutions Collaborate to Speed Manufacturing of mmWave Semiconductors
November 26, 2019
Imperas delivers highest quality RISC-V RV32I compliance test suites to implementers and adopters of RISC-V
November 21, 2019
UVM-AMS Working Group Formed to Standardize UVM Analog/Mixed-Signal Extensions
November 20, 2019
SmartDV’s Platform-Independent VIP Portfolio Ensures Seamless Coverage-Driven Verification Flow
November 19, 2019
Graphcore leveraged Mentor’s Questa technologies to verify massive Colossus GC2 AI processor
November 14, 2019
New Cadence UltraLink D2D PHY IP for Die-to-Die Connectivity Enables High-Performance Applications with Cost-Effective Packaging
eSilicon to be Acquired by Inphi and Synopsys
November 13, 2019
Mentor introduces Tessent Safety ecosystem to meet IC test requirements of the autonomous vehicles era
November 12, 2019
Mentor’s Tessent Connect automation reduces IC test implementation costs and accelerates time to market
November 7, 2019
Cadence Announces Tempus Power Integrity Solution for Signoff Timing-Aware IR Drop Analysis
November 6, 2019
GLOBALFOUNDRIES and SiFive to Deliver Next Level of High Bandwidth Memory on 12LP Platform for AI Applications
Optima Design Automation Launches with Focus on Next-Generation Semiconductor Functional Safety Tools
October 31, 2019
NSITEXE Achieves First-Pass Silicon Success for High-Performance Data Flow Processor-based SoC Test Chip Using DesignWare IP
October 29, 2019
GLOBALFOUNDRIES and TSMC Announce Resolution of Global Disputes Through Broad Global Patent Cross-License
October 22, 2019
Synopsys Launches New ARC VPX DSP Processor IP for High-performance Signal Processing SoC Designs
Cadence Announces First-to-Market NVMe 1.4 Verification IP for High-Performance Computing
News Archive →
featured blogs
Memory Summary
Jan 17, 2020
[From the last episode: We saw how virtual memory helps resolve the differences between where a compiler thinks things will go in memory and the real memories in a real system.] We'€™ve talked a lot about memory '€“ different kinds of memory, cache memory, heap memory, vi...
More from Inside the IoT...
Build a High-Speed Cable in Under a Minute with our Upgraded High-Speed Cable Builder
Jan 16, 2020
While Samtec started as a connector company with a focus on two-piece, pin-and-socket board stacking systems, High-Speed Board Stacking connectors and High-Speed Cable Assemblies now make up a significant portion of our sales. To support development in this area, in December ...
More from Samtec, Inc....
Article Roundup: Hydrogen Powered Cars, On-Demand DRC with P&R, AV SoC Functional Safety, Automating CDC Verification & Advanced Packaging LVS and LVL issues
Jan 16, 2020
Betting on Hydrogen-Powered Cars On-demand DRC within P&R cuts closure time in half for MaxLinear Functional Safety Verification For AV SoC Designs Accelerated With Advanced Tools Automating the pain out of clock domain crossing verification Mentor unpacks LVS and LVL iss...
More from Mentor...
DIY International Space Station Tracker
Jan 16, 2020
This little robot arm continually points to the current location of the International Space Station (ISS)....
More from Max's Cool Beans...
chalk talks
Wide Band Gap: Silicon Carbide — ON Semiconductor and Mouser Electronics  Wide bandgap materials such as silicon carbide are revolutionizing the power industry. From electric vehicles and charging stations to solar power to industrial power supplies, wide bandgap brings efficiency, improved thermal performance, size reduction, and more. In this episode of Chalk Talk, Amelia Dalton chats with Brandon Becker from ON Semiconductor about the advantages … Read More → "Wide Band Gap: Silicon Carbide — ON Semiconductor and Mouser Electronics"
Accelerating Physical Verification Productivity   Physical verification can take an enormous amount of time, and catching errors early in the process is the best way to avoid costly and time-consuming iterations. In this episode of Chalk Talk, Amelia Dalton chats with Christen Decoin of Synopsys about accelerating physical design productivity with tools and methods that can help catch … Read More → "Accelerating Physical Verification Productivity"
Tensilica HiFi DSP   Performing speech recognition at the edge, rather than sending data back to the cloud, is a major engineering challenge. You need significant processing power on a tiny energy budget, and often in a small form-factor. In this episode of Chalk Talk, Amelia Dalton chats with Gerard Andrews of Cadence Design Systems about the … Read More → "Tensilica HiFi DSP"
Overcoming Today’s RFIC and SiP Design Challenges with Virtuoso RF Solution   5G presents daunting challenges for RF design. RF modules are reaching a level of complexity such that verification and analysis now demand about half of the design time, and that requires an integrated flow including physical verification and analysis as well as circuit design. In this episode of Chalk Talk, Amelia Dalton chats … Read More → "Overcoming Today’s RFIC and SiP Design Challenges with Virtuoso RF Solution"
Introducing Cadence Cloud Portfolio  EDA in the cloud has finally arrived! Now, when you need access to large amounts of computing power to push your design through those critical stages, there is a secure, reliable, powerful cloud-based system that lets you scale your design tools to meet your actual needs. In this episode of Chalk Talk, Amelia Dalton … Read More → "Introducing Cadence Cloud Portfolio"
What is Intel® Optane™ Technology? — Mouser Electronics and Intel  Memory architecture is often the biggest bottleneck in a high-performance system design. The gap between high-speed DRAM and higher-capacity non-volatile memory sits at an inconvenient place on the cost-performance curve. In this episode of Chalk Talk, Amelia Dalton chats with Jeffrey Galinovsky of Intel about how new Intel technologies including Intel® Optane™ memory technology … Read More → "What is Intel® Optane™ Technology? — Mouser Electronics and Intel"
Chalk Talk Archive →