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High-Speed Communications: Not Just Binary Anymore

Flash memory technologists had a problem. Their customers needed more memory, and so they were trying to make the memory cells smaller so they could fit more onto a chip. But the demand was growing faster than the technology was shrinking, so they needed to get to higher densities more quickly.

The basic flash memory cell had … Read More → "High-Speed Communications: Not Just Binary Anymore"

Staying Too Long at the Faire

It’s a sad day. Maker Media, Inc. ceased operations this week and laid off all staff. The company published Make: magazine and operated and licensed “Maker Faires” around the world. We have covered the maker movement and Maker Faires for years, even though our audience is professional engineers. We saw value there. Maker Faire was a window into the future of engineering – a place where we could go … Read More → "Staying Too Long at the Faire"

DAC At It (Again)

The intrepid EE Journal team is back (and taking no prisoners) at this year’s Design Automation Conference in Las Vegas, Nevada. First up, we chat with the DAC Monday keynote speaker Galen Hunt (Microsoft – Distinguished Engineer and Managing Director, Microsoft Azure Sphere). Galen and I chat about the seven properties of secure devices and why he thinks IOT isn’t a technology revolution. Next up, … Read More → "DAC At It (Again)"

Achronix 7nm Speedster7t FPGAs

We’ve always been pretty impressed by Achronix – and for good reason. In an FPGA market where countless startups have tried and failed, Achronix somehow built themselves into a successful, independent, profit-making FPGA company. That’s not an easy task, and it required numerous “pivots” on the part of the company.

Initially, Achronix developed a family of novel asynchronous FPGAs and associated tools. When it became clear … Read More → "Achronix 7nm Speedster7t FPGAs"

Firming Up Your Photoresist

When you spend a goodly chunk of your career dealing with EDA-like issues, as did I, then you have a pretty easy gut reaction to anything involving synthesis. See some kind of synthesis with a fancy new name? Must be some new crazy approach to generating logic circuits, right? Probably involving AI (which everything must have these days)?

Um… no. … Read More → "Firming Up Your Photoresist"

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featured blogs
Jun 17, 2019
One topic that garnered much interest at the Samtec booth at the International Microwave Symposium was a dynamic stress test of Samtec’s microwave cable. This demonstration proves that our low-loss, microwave cable withstands high flex cycles and still maintains signal ...
Jun 17, 2019
You know what it's like, right? Those sudden urges to declutter the house. Well, during one such exercise, my niece stumbled across some cassettes and looked at them like they were from some... [[ Click on the title to access the full blog on the Cadence Community site....
Jun 14, 2019
By Flint Yoder – Mentor, A Siemens Business Tight schedules? Worried about product reliability? Now you can find and eliminate latch-up sensitivity during schematic design, and avoid those post-layout nightmares. Latch-up'€¦the bane of circuit designers and circuit ve...
Jan 25, 2019
Let'€™s face it: We'€™re addicted to SRAM. It'€™s big, it'€™s power-hungry, but it'€™s fast. And no matter how much we complain about it, we still use it. Because we don'€™t have anything better in the mainstream yet. We'€™ve looked at attempts to improve conven...
chalk talks
Accelerating Physical Verification Productivity   Physical verification can take an enormous amount of time, and catching errors early in the process is the best way to avoid costly and time-consuming iterations. In this episode of Chalk Talk, Amelia Dalton chats with Christen Decoin of Synopsys about accelerating physical design productivity with tools and methods that can help catch … Read More → "Accelerating Physical Verification Productivity"
Tensilica HiFi DSP   Performing speech recognition at the edge, rather than sending data back to the cloud, is a major engineering challenge. You need significant processing power on a tiny energy budget, and often in a small form-factor. In this episode of Chalk Talk, Amelia Dalton chats with Gerard Andrews of Cadence Design Systems about the … Read More → "Tensilica HiFi DSP"
Overcoming Today’s RFIC and SiP Design Challenges with Virtuoso RF Solution   5G presents daunting challenges for RF design. RF modules are reaching a level of complexity such that verification and analysis now demand about half of the design time, and that requires an integrated flow including physical verification and analysis as well as circuit design. In this episode of Chalk Talk, Amelia Dalton chats … Read More → "Overcoming Today’s RFIC and SiP Design Challenges with Virtuoso RF Solution"
Introducing Cadence Cloud Portfolio  EDA in the cloud has finally arrived! Now, when you need access to large amounts of computing power to push your design through those critical stages, there is a secure, reliable, powerful cloud-based system that lets you scale your design tools to meet your actual needs. In this episode of Chalk Talk, Amelia Dalton … Read More → "Introducing Cadence Cloud Portfolio"
What is Intel® Optane™ Technology? — Mouser Electronics and Intel  Memory architecture is often the biggest bottleneck in a high-performance system design. The gap between high-speed DRAM and higher-capacity non-volatile memory sits at an inconvenient place on the cost-performance curve. In this episode of Chalk Talk, Amelia Dalton chats with Jeffrey Galinovsky of Intel about how new Intel technologies including Intel® Optane™ memory technology … Read More → "What is Intel® Optane™ Technology? — Mouser Electronics and Intel"
A New Advanced IC Packaging Battlefield  Today, advanced packaging technology has created a new battleground where 2.5D packaging and heterogeneous design drive constraints that span semiconductor, packaging, board, and even system-level design. In this episode of Chalk Talk, Amelia Dalton chats with John Park of Cadence Design Systems about new techniques and tools for advanced IC packaging design. Click here … Read More → "A New Advanced IC Packaging Battlefield"