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Modernizing the Memory Hierarchy

We now live in a data-driven world. With the proliferation of IoT, we are rapidly ramping toward a trillion connected sensors on the planet, all gathering data at an ever-accelerating pace. In just the last year or so, it is likely that we have gathered more data than in all of human history prior to that. But data is useless unless we do something with it, … Read More → "Modernizing the Memory Hierarchy"

In the Shadow of Moore’s Law

For the last half century, a large segment of the world’s electronic engineers have worked in the insane vortex of Moore’s Law. Entire engineering careers from college through retirement have been spent with the only constant being exponential change. Whatever you learned in engineering school was obsolete before your first job promotion. Whatever you managed to design one year, you had to double to … Read More → "In the Shadow of Moore’s Law"

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featured blogs
Feb 15, 2019
Monday is Presidents' Day, and Cadence (in the US) will be off for the day. Breakfast Bytes will be off too, and as is now traditional, the post before the break is about whatever I feel like.... [[ Click on the title to access the full blog on the Cadence Community sit...
Feb 15, 2019
This year at DVCon US, Mentor is going to add some sizzle to our booth (#1005) during the exhibit hours. In addition to our stellar demo staff who are always available to answer questions and show you the latest capabilities of our tools, we’re also going to be hosting ...
Feb 14, 2019
Samtec'€™s complete line of discrete wire connectors and cable assemblies are used in a variety of applications, including industrial automation, industrial equipment, security, telecom, automation, controls, military and defense, and transportation, to name a few. Samtec d...
Jan 25, 2019
Let'€™s face it: We'€™re addicted to SRAM. It'€™s big, it'€™s power-hungry, but it'€™s fast. And no matter how much we complain about it, we still use it. Because we don'€™t have anything better in the mainstream yet. We'€™ve looked at attempts to improve conven...
chalk talks
Introducing Cadence Cloud Portfolio  EDA in the cloud has finally arrived! Now, when you need access to large amounts of computing power to push your design through those critical stages, there is a secure, reliable, powerful cloud-based system that lets you scale your design tools to meet your actual needs. In this episode of Chalk Talk, Amelia Dalton … Read More → "Introducing Cadence Cloud Portfolio"
What is Intel® Optane™ Technology? — Mouser Electronics and Intel  Memory architecture is often the biggest bottleneck in a high-performance system design. The gap between high-speed DRAM and higher-capacity non-volatile memory sits at an inconvenient place on the cost-performance curve. In this episode of Chalk Talk, Amelia Dalton chats with Jeffrey Galinovsky of Intel about how new Intel technologies including Intel® Optane™ memory technology … Read More → "What is Intel® Optane™ Technology? — Mouser Electronics and Intel"
A New Advanced IC Packaging Battlefield  Today, advanced packaging technology has created a new battleground where 2.5D packaging and heterogeneous design drive constraints that span semiconductor, packaging, board, and even system-level design. In this episode of Chalk Talk, Amelia Dalton chats with John Park of Cadence Design Systems about new techniques and tools for advanced IC packaging design. Click here … Read More → "A New Advanced IC Packaging Battlefield"
Designing High-Reliability Analog and Mixed-Signal ICs for Mission-Critical Applications  Designing products for reliability and longevity requires a different mindset – and a different tool set from the more common “just get it out the door” engineering methodology. We need to focus on all phases of product life, and do a diligent analysis of the mechanisms that can lead to premature failure in the … Read More → "Designing High-Reliability Analog and Mixed-Signal ICs for Mission-Critical Applications"
Scaling Up Vision and AI DSP Performance  For high-performance, low-power processing of AI and machine vision algorithms, latency can be critical. In this episode of Chalk Talk, Amelia Dalton chats with Pulin Desai from Cadence Design Systems about the using the new Vision Q6 processor core for embedded vision and AI applications. Click here for more information about Vision DSPs for … Read More → "Scaling Up Vision and AI DSP Performance"
Debug and Verify FPGA Algorithms with MATLAB and Simulink   Today’s FPGA designs require industrial-strength functional verification. The ad-hoc methods that worked with older, smaller FPGAs just don’t cut it anymore. In this episode of Chalk Talk, Amelia Dalton chats with Eric Cigan of MathWorks about ASIC-strength functional verification with model-based design. Click here for more information about how to verify VHDL and … Read More → "Debug and Verify FPGA Algorithms with MATLAB and Simulink"