Semiconductor
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IP Market Large, Growing, and Strange

The semiconductor IP market is big, growing, lopsided, lumpy, and weird.

What it’s not is particularly lucrative. Which is odd, considering that you’re selling the rights to intangible goods and collecting royalties on that in perpetuity. At first blush, it’s like printing money, just without the money part.

The total IP market raked in somewhere around Read More → "IP Market Large, Growing, and Strange"

Group Puzzles Out Silicon Specs

Someday, a new class of semiconductor companies will assemble their products Lego-style, mixing and matching dice from multiple companies. It’s a huge change that’s still a long way off.

More than 146 people from 80 companies signed up for an event last week at IBM’s Almaden Research Center to take some small steps in this direction. It was the … Read More → "Group Puzzles Out Silicon Specs"

High-End FPGA Showdown – Part 1

Intel announced this week that they have begun shipping the first of their new Agilex FPGAs to early-access customers.  This moves us into what we historically think of as the “head-to-head” phase of the competition between the two biggest FPGA suppliers. Xilinx shipped their first “Versal ACAP” FPGAs back in June, so, after a very long and contentious “who is going to ship first?” battle, it … Read More → "High-End FPGA Showdown – Part 1"

Goldilocks Process Windows

One of the tricky bits when launching a new process is figuring out what the process window is.  For anyone new to the concept, the window is the range of variation that’s allowable for a given process parameter. Go outside that range, and a die – or a wafer – or a lot – may fail. It’s best if you can have a wide window, because then … Read More → "Goldilocks Process Windows"

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featured blogs
Oct 16, 2019
In this week's Whiteboard Wednesdays video, David Peña discusses Cadence'€™s focus on models for various emerging memory standards. https://youtu.be/_Xps6I6kE0E [[ Click on the title to access the full blog on the Cadence Community site. ]]...
Oct 15, 2019
As technology advances, it's becoming harder and harder to know what is real and what isn't....
Oct 14, 2019
My working life includes a lot of writing – blogs, articles, conference papers and white papers are typical of what I produce. A common factor of my writing is that it is aimed to be technical and instructive. What I do not like writing is sales pitches. I can accept th...
Oct 14, 2019
In 1995, I attended a seminar in which the presenter told us that copper was dead.  This sort of statement is not new. The connector market is filled with armchair pundits who predict the demise of everything from D-Subminiature connectors (which are very much alive and ...
Oct 11, 2019
[From the last episode: We looked at subroutines in computer programs.] We saw a couple weeks ago that some memories are big, but slow (flash memory). Others are fast, but not so big '€“ and they'€™re power-hungry to boot (SRAM). This sets up an interesting problem. When ...
chalk talks
Accelerating Physical Verification Productivity   Physical verification can take an enormous amount of time, and catching errors early in the process is the best way to avoid costly and time-consuming iterations. In this episode of Chalk Talk, Amelia Dalton chats with Christen Decoin of Synopsys about accelerating physical design productivity with tools and methods that can help catch … Read More → "Accelerating Physical Verification Productivity"
Tensilica HiFi DSP   Performing speech recognition at the edge, rather than sending data back to the cloud, is a major engineering challenge. You need significant processing power on a tiny energy budget, and often in a small form-factor. In this episode of Chalk Talk, Amelia Dalton chats with Gerard Andrews of Cadence Design Systems about the … Read More → "Tensilica HiFi DSP"
Overcoming Today’s RFIC and SiP Design Challenges with Virtuoso RF Solution   5G presents daunting challenges for RF design. RF modules are reaching a level of complexity such that verification and analysis now demand about half of the design time, and that requires an integrated flow including physical verification and analysis as well as circuit design. In this episode of Chalk Talk, Amelia Dalton chats … Read More → "Overcoming Today’s RFIC and SiP Design Challenges with Virtuoso RF Solution"
Introducing Cadence Cloud Portfolio  EDA in the cloud has finally arrived! Now, when you need access to large amounts of computing power to push your design through those critical stages, there is a secure, reliable, powerful cloud-based system that lets you scale your design tools to meet your actual needs. In this episode of Chalk Talk, Amelia Dalton … Read More → "Introducing Cadence Cloud Portfolio"
What is Intel® Optane™ Technology? — Mouser Electronics and Intel  Memory architecture is often the biggest bottleneck in a high-performance system design. The gap between high-speed DRAM and higher-capacity non-volatile memory sits at an inconvenient place on the cost-performance curve. In this episode of Chalk Talk, Amelia Dalton chats with Jeffrey Galinovsky of Intel about how new Intel technologies including Intel® Optane™ memory technology … Read More → "What is Intel® Optane™ Technology? — Mouser Electronics and Intel"
A New Advanced IC Packaging Battlefield  Today, advanced packaging technology has created a new battleground where 2.5D packaging and heterogeneous design drive constraints that span semiconductor, packaging, board, and even system-level design. In this episode of Chalk Talk, Amelia Dalton chats with John Park of Cadence Design Systems about new techniques and tools for advanced IC packaging design. Click here … Read More → "A New Advanced IC Packaging Battlefield"