This week we take on a couple of developments in the MRAM world. While much of our more recent MRAM coverage has focused on the newer (and not yet ready for production) SOT (spin-orbit torque) approach, today’s stories are rooted in the more common (and now in production) STT (spin-transfer torque) technology.
Testing the Magnetics
… Read More → "MRAM Testing and Solderability"
The semiconductor IP market is big, growing, lopsided, lumpy, and weird.
What it’s not is particularly lucrative. Which is odd, considering that you’re selling the rights to intangible goods and collecting royalties on that in perpetuity. At first blush, it’s like printing money, just without the money part.
The total IP market raked in somewhere around Read More → "IP Market Large, Growing, and Strange"
Someday, a new class of semiconductor companies will assemble their products Lego-style, mixing and matching dice from multiple companies. It’s a huge change that’s still a long way off.
More than 146 people from 80 companies signed up for an event last week at IBM’s Almaden Research Center to take some small steps in this direction. It was the … Read More → "Group Puzzles Out Silicon Specs"
Intel announced this week that they have begun shipping the first of their new Agilex FPGAs to early-access customers. This moves us into what we historically think of as the “head-to-head” phase of the competition between the two biggest FPGA suppliers. Xilinx shipped their first “Versal ACAP” FPGAs back in June, so, after a very long and contentious “who is going to ship first?” battle, it … Read More → "High-End FPGA Showdown – Part 1"
Two ongoing questions have plagued analog design for many years:
- How can we design analog circuits more quickly and more portably?
- How can we keep up with the growth in circuit size while still providing gold-standard sign-off simulation in a “reasonable” time? The meaning of “reasonable” being somewhat fluid…</ … Read More → "Analog Advancements"
One of the tricky bits when launching a new process is figuring out what the process window is. For anyone new to the concept, the window is the range of variation that’s allowable for a given process parameter. Go outside that range, and a die – or a wafer – or a lot – may fail. It’s best if you can have a wide window, because then … Read More → "Goldilocks Process Windows"