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The Next Generation of Process Engineering: How Human-Machine Collaboration Will Usher In A New Era of Chip Innovation

In this week’s Fish Fry podcast, I’m going deep into the world of atomic-level process engineering with Keren Kanarik from Lam Research. Keren and I discuss how artificial intelligence can help speed up the process and lower the cost of chip innovation. We also investigate the engineering and AI challenges this research was looking to solve and the strategies that Keren and her team at Lam Research … Read More → "The Next Generation of Process Engineering: How Human-Machine Collaboration Will Usher In A New Era of Chip Innovation"

Boosting Semiconductor Fab Productivity by up to 20 Percent!

In the microelectronics industry, the term “semiconductor fabrication plant” (a.k.a. “semiconductor fab”; sometimes called a “foundry”) is a factory for semiconductor device fabrication. In layman’s terms, this is where they build the silicon chips that power our modern world. Even a small fab can easily cost $1 billion. Spending $3 to $5 billion is not uncommon, and you can splash a lot … Read More → "Boosting Semiconductor Fab Productivity by up to 20 Percent!"

Edward Keonjian: The High-IQ, Armenian-American Forrest Gump of Microelectronics, Part 1

The 1986 novel Forrest Gump and the 1994 movie based on the novel depicted a man who was present at many significant events in the 20th century. In that same way, Edward Keonjian managed to be closely associated with many developments in electronics, especially microelectronics. The fictitious character Forrest Gump supposedly had a low IQ, but he loved meeting people. The very real Edward Keonjian also loved meeting people, and he clearly had very high intelligence. … Read More → "Edward Keonjian: The High-IQ, Armenian-American Forrest Gump of Microelectronics, Part 1"

Doing the Time Warp with Calibre DesignEnhancer

When I worked on my first ASIC deep in the mists of time that we used to call the 1980s, we employed a traditional “waterfall” model for our design and verification flows. In this case, any activities associated with the project were broken down into linear sequential phases, where each phase depended on the deliverables from the previous one.

The … Read More → "Doing the Time Warp with Calibre DesignEnhancer"

Ray Holt and the Lost History of the First Multi-Chip Microprocessor

During a Zoom meeting of the Computer History Museum’s (CHM) SemiSIG earlier this year, our fearless leader Doug Fairbairn mentioned that he was having trouble contacting Ray Holt to arrange a recording of his oral history. CHM’s SemiSIG records oral histories of past and present luminaries in the semiconductor industry, and Holt’s history is a rich one. After getting his EE degree at Cal … Read More → "Ray Holt and the Lost History of the First Multi-Chip Microprocessor"

Where Rubber Meets The Road: Simulation, AI Modeling, and The Future of the Automotive Industry

This week’s Fish Fry podcast is all about AI modeling for automotive applications.  Seth DeLand (MathWorks) and I discuss the common challenges that automotive engineers face when implementing simulation into AI modeling, which automotive applications would benefit most from simulation, and why data preparation is a crucial step in the AI workflow during model-based design for automotive … Read More → "Where Rubber Meets The Road: Simulation, AI Modeling, and The Future of the Automotive Industry"

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featured blogs
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chalk talks
One Year of Synopsys Cloud: Adoption, Enhancements and Evolution — Synopsys  The adoption of the cloud in the design automation industry has encouraged innovation across the entire semiconductor lifecycle. In this episode of Chalk Talk, Amelia Dalton chats with Vikram Bhatia from Synopsys about how Synopsys is redefining EDA in the Cloud with the industry’s first complete browser-based EDA-as-a-Service cloud platform. They explore the benefits … Read More → "One Year of Synopsys Cloud: Adoption, Enhancements and Evolution — Synopsys"
Automated Benchmark Tuning — Synopsys   Benchmarking is a great way to measure the performance of computing resources, but benchmark tuning can be a very complicated problem to solve. In this episode of Chalk Talk, Nozar Nozarian from Synopsys and Amelia Dalton investigate Synopsys’ Optimizer Studio that combines an evolution search algorithm with a powerful user interface that can … Read More → "Automated Benchmark Tuning — Synopsys"
Chipageddon: What’s Happening, Why It’s Happening and When Will It End — Digi & Mouser Electronics  Semiconductors are an integral part of our design lives, but supply chain issues continue to upset our design processes. In this episode of Chalk Talk, Ronald Singh from DIGI and Amelia Dalton investigate the variety of reasons behind today’s semiconductor supply chain woes. They also take a closer look at how a system-on-module approach … Read More → "Chipageddon: What’s Happening, Why It’s Happening and When Will It End — Digi & Mouser Electronics"
Enabling Digital Transformation in Electronic Design with Cadence Cloud — Cadence  With increasing design sizes, complexity of advanced nodes, and faster time to market requirements – design teams are looking for scalability, simplicity, flexibility and agility. In today’s Chalk Talk, Amelia Dalton chats with Mahesh Turaga from Cadence Design Systems about the details of Cadence’s end to end cloud portfolio, how you can extend your … Read More → "Enabling Digital Transformation in Electronic Design with Cadence Cloud — Cadence"
Faster, More Predictable Path to Multi-Chiplet Design Closure — Cadence Design Systems  The challenges for 3D IC design are greater than standard chip design – but they are not insurmountable. In this episode of Chalk Talk, Amelia Dalton chats with Vinay Patwardhan from Cadence Design Systems about the variety of challenges faced by 3D IC designers today and how Cadence’s integrated, high-capacity Integrity 3D IC Platform, … Read More → "Faster, More Predictable Path to Multi-Chiplet Design Closure — Cadence Design Systems"
“Scalable Power Delivery” for High-Performance ASICs, SoCs, and xPUs — Infineon  Today’s AI and Networking applications are driving an exponential increase in compute power. When it comes to scaling power for these kinds of applications with next generation chipsets, we need to keep in mind package size constraints, dynamic current balancing, and output capacitance. In this episode of Chalk Talk, Mark Rodrigues from Infineon joins … Read More → "“Scalable Power Delivery” for High-Performance ASICs, SoCs, and xPUs — Infineon"