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The Significance of Sparsity

What has sparsity done for you lately? In this episode of Fish Fry, we investigate the challenges that surround on-device artificial intelligence processing. Megha Daga (Cadence Design Systems) and I discuss the why the presence of zeroes is becoming more and more important in the development of neural networks and how sparsity can be used for bandwidth and compute reduction. In this week’s News You May Have Missed, … Read More → "The Significance of Sparsity"

Xilinx Scores Azure Acceleration Win

Xilinx scored a major win recently, with Microsoft’s Azure cloud group reportedly making a commitment to use Xilinx devices in something like half of their future Azure deployments. Until now, Azure has been solidly in the Intel PSG (Altera) camp for FPGA-based acceleration. Microsoft says that every Azure server for the past several years has been equipped with FPGAs, and, until now, those … Read More → "Xilinx Scores Azure Acceleration Win"

Operation: SIM

“Captain’s log, Stardate 4211.4. Keeping our presence here secret… is an enormous tactical advantage.” – Captain Kirk

In this week’s episode of Fish Fry, we take a closer look at security in IoT devices with a little help from Rich Collins from Synopsys. Rich and I chat about the challenges of the SIM product lifecycle and why pre-verified hardware and software can make all the … Read More → "Operation: SIM"

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featured blogs
Nov 16, 2018
If you aren'€™t from the packaging world, then chances are likely you might think '€œpacking'€ refers to objects being placed in to a box instead of packaging integrated circuits (IC'€™s) on a substrate. Packaging has advanced since it began, and as with many areas i...
Nov 14, 2018
  People of a certain age, who mindfully lived through the early microcomputer revolution during the first half of the 1970s, know about Bill Godbout. He was that guy who sent out crudely photocopied parts catalogs for all kinds of electronic components, sold from a Quon...
Nov 13, 2018
Podcast Interview with the authors of The Hitchhikers Guide to PCB Design eBook by Mike Beutow with PCB Chat....
chalk talks
A New Advanced IC Packaging Battlefield  Today, advanced packaging technology has created a new battleground where 2.5D packaging and heterogeneous design drive constraints that span semiconductor, packaging, board, and even system-level design. In this episode of Chalk Talk, Amelia Dalton chats with John Park of Cadence Design Systems about new techniques and tools for advanced IC packaging design. Click here … Read More → "A New Advanced IC Packaging Battlefield"
Designing High-Reliability Analog and Mixed-Signal ICs for Mission-Critical Applications  Designing products for reliability and longevity requires a different mindset – and a different tool set from the more common “just get it out the door” engineering methodology. We need to focus on all phases of product life, and do a diligent analysis of the mechanisms that can lead to premature failure in the … Read More → "Designing High-Reliability Analog and Mixed-Signal ICs for Mission-Critical Applications"
Scaling Up Vision and AI DSP Performance  For high-performance, low-power processing of AI and machine vision algorithms, latency can be critical. In this episode of Chalk Talk, Amelia Dalton chats with Pulin Desai from Cadence Design Systems about the using the new Vision Q6 processor core for embedded vision and AI applications. Click here for more information about Vision DSPs for … Read More → "Scaling Up Vision and AI DSP Performance"
Debug and Verify FPGA Algorithms with MATLAB and Simulink   Today’s FPGA designs require industrial-strength functional verification. The ad-hoc methods that worked with older, smaller FPGAs just don’t cut it anymore. In this episode of Chalk Talk, Amelia Dalton chats with Eric Cigan of MathWorks about ASIC-strength functional verification with model-based design. Click here for more information about how to verify VHDL and … Read More → "Debug and Verify FPGA Algorithms with MATLAB and Simulink"
Mixed-Signal Digital Complexity Explosion   Mixed-signal design is becoming increasingly complex, and our old tools and methods just won’t cut it. In this episode of Chalk Talk, Amelia Dalton chats with Rod Metcalfe of Cadence Design Systems about the changing mixed-signal landscape and how Cadence’s robust suite of mixed-signal design solutions can solve your toughest problems. Click here … Read More → "Mixed-Signal Digital Complexity Explosion"
Moving Between FPGA and ASIC with High-Level Synthesis Writing RTL that works smoothly on both FPGA and ASIC implementations is nearly impossible. But, High-Level Synthesis (HLS) can make technology-independent design a breeze. In this episode of Chalk Talk, Amelia Dalton chats with Stuart Clubb of Mentor’s Catapult team about how to use HLS to accelerate your design flow. Click here for more … Read More → "Moving Between FPGA and ASIC with High-Level Synthesis"