With the promises and challenges of artificial intelligence (AI) and, more specifically, machine learning (ML), this is a time of great architectural innovation as developers compete to provide the best ML solutions. All engineering solutions have trade-offs; the trick here is to find the solution(s) with the fewest bad trade-offs.
In Part 1 of this series, we looked at the new high-end FPGA families from Achronix, Intel, and Xilinx. We compared the underlying semiconductor processes, the type and amount of programmable logic LUT fabric, the type and amount of DSP/arithmetic resources and their applicability to AI inference acceleration tasks, the claimed TOPS/FLOPS performance capabilities, and on-chip interconnect such as FPGA routing resources and networks-on-chip (NOCs). From those comparisons it is clear that each of these vendors’ offerings has unique and interesting capabilities … Read More → "High-End FPGA Showdown – Part 2"
[A previous version of this article contained a metaphor to watching pornography which has been removed, with our apologies.]
For two days in late August, an estimated 1,000 engineers crowded into Stanford Memorial Hall in Palo Alto, Calif. for Hot Chips 2019. #HotChips19, aka #HotChips31, featured some of the most impressive microprocessors seen in Silicon Valley in some time. That’s because we are in a new golden age of chip architecture, according to tech gurus John Hennessy and David A. Patterson, who co-wrote a leading … Read More → "Hot Chips 2019"
“I’m not deaf. I’m ignoring you.” T-shirt wisdom
Devo and The Tubes warned us this would happen: it’s de-evolution, or the completion backwards principle. We’re regressing. It’s not our imagination. Our computers really are getting slower.
Okay, so maybe not the entire computer, but one important part of nearly every modern machine is slower – a lot slower – than computers of two or three decades ago.
At this summer’s DAC conference, Mentor had a couple of artificial intelligence (AI)-related announcements. One of them concerned their own use of AI for physical chip verification, which we have already covered. The other dealt with tools and blocks for use by engineers designing AI architectures, and that’s … Read More → "Neural Network Notions and Tools"
Intel announced this week that they have begun shipping the first of their new Agilex FPGAs to early-access customers. This moves us into what we historically think of as the “head-to-head” phase of the competition between the two biggest FPGA suppliers. Xilinx shipped their first “Versal ACAP” FPGAs back in June, so, after a very long and contentious “who is going to ship first?” battle, it turns out the two rival companies began shipping their comparable FPGA lines within about two months of each other. This means that, unlike other recent races to be first on … Read More → "High-End FPGA Showdown – Part 1"
“Never attribute to malice that which can be adequately explained by stupidity.” — Hanlon’s razor
You may remember them. A young newlywed couple cancelled their big honeymoon plans because the trip got too expensive. They’d spent months preparing for a big driving trip from their home in southern California up north to San Francisco, Monterey, and Napa Valley, hitting all the usual tourist spots. But in a tearful interview, the new bride said they’d had to cancel the trip because gas prices had gotten too high, busting their budget. Instead, … Read More → "Why Engineers Don’t Set Prices"
Two ongoing questions have plagued analog design for many years:
- How can we design analog circuits more quickly and more portably?
- How can we keep up with the growth in circuit size while still providing gold-standard sign-off simulation in a “reasonable” time? The meaning of “reasonable” being somewhat fluid…
At this summer’s DAC, I had a couple of conversations, each dealing with one of these questions. No Holy Grails have been … Read More → "Analog Advancements"
“With great power comes great responsibility.” – Uncle Ben
Nah, me neither. But now it can be yours. For free. Srsly.
IBM has released the Power Architecture instruction set to the Linux Foundation, making it freely available to anyone who wants it. It’s a no-cost, royalty-free license to the ISA much like the one for RISC-V and other open-source processors. Starting now, you can design your own PowerPC processor without first paying a hefty … Read More → "IBM Gives Away PowerPC; Goes Open Source"
One of the tricky bits when launching a new process is figuring out what the process window is. For anyone new to the concept, the window is the range of variation that’s allowable for a given process parameter. Go outside that range, and a die – or a wafer – or a lot – may fail. It’s best if you can have a wide window, because then you can tolerate lots of variability. If the window is too narrow, then you’re spending all your time trying to thwart that variation and keep the equipment in the … Read More → "Goldilocks Process Windows"