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The Challenge of Systemic Complexity

We’re tackling the multi-faceted challenges of embedded software development in this week’s episode of Amelia’s Weekly Fish Fry. Simon Davidmann (CEO – Imperas) joins us to discuss how familiar debug environments can make all the difference in complex designs and why RISC-V architecture is gaining traction in the EE ecosystem. Next up, Rupert Baines (CEO – UltraSoC) joins us to chat about the details of their “Smart Monitor” … Read More → "The Challenge of Systemic Complexity"

Adventures in Micro Land

In this week’s Fish Fry, we’re following a microcontroller yellow brick road to a land where analog reigns supreme. Dave Smith (Texas Instruments) joins us to discuss the details of the “Smart Analog Combo” included in in the MSP430 family, the benefits of the configurable signal-chain elements inherent in this solution, and why the … Read More → "Adventures in Micro Land"

Full-Power WiFi at Half the Power

In IoTland, communication is king. It puts the Internet in the IoT. But how to communicate? LTE? BlueTooth? WiFi? It partly depends on the application and the location, but it also depends on how far you are from a wall plug.

Because many IoT devices are small, portable, and – this is key – battery-powered, they will forever be infinitely far away from the wall plug. While WiFi has … Read More → "Full-Power WiFi at Half the Power"

Let’s Get (a) Physical

“UNIX is basically a simple operating system, but you have to be a genius to understand the simplicity.” — Dennis Ritchie

You can turn a sailboat around faster than a battleship, and a minnow changes course quicker than a whale. Small-fry RTOS company RoweBots has made a sharp pivot and set its compass toward bright horizons in the medical-devices field.

If you’ve heard … Read More → "Let’s Get (a) Physical"

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featured blogs
Aug 17, 2018
If you read my post Who Put the Silicon in Silicon Valley? then you know my conclusion: Let's go with Shockley. He invented the transistor, came here, hired a bunch of young PhDs, and sent them out (by accident, not design) to create the companies, that created the compa...
Aug 16, 2018
All of the little details were squared up when the check-plots came out for "final" review. Those same preliminary files were shared with the fab and assembly units and, of course, the vendors have c...
Aug 15, 2018
VITA 57.4 FMC+ Standard As an ANSI/VITA member, Samtec supports the release of the new ANSI/VITA 57.4-2018 FPGA Mezzanine Card Plus Standard. VITA 57.4, also referred to as FMC+, expands upon the I/O capabilities defined in ANSI/VITA 57.1 FMC by adding two new connectors that...
Aug 14, 2018
I worked at HP in Ft. Collins, Colorado back in the 1970s. It was a heady experience. We were designing and building early, pre-PC desktop computers and we owned the market back then. The division I worked for eventually migrated to 32-bit workstations, chased from the deskto...
Jul 30, 2018
As discussed in part 1 of this blog post, each instance of an Achronix Speedcore eFPGA in your ASIC or SoC design must be configured after the system powers up because Speedcore eFPGAs employ nonvolatile SRAM technology to store its configuration bits. The time required to pr...