In my previous column — What the FAQ are CPUs, MPUs, MCUs, and GPUs? — we discussed the fact that the electronics industry is replete with acronyms, especially the three-letter variety. We also noted that we tend to learn a lot of things by osmosis, gradually ( … Read More → "What the FAQ are ASICs, ASSPs, SoCs, SOMs, etc.?"
What do high level synthesis, FPGAs, and the first 3D printer capable of printing fully-functional electronics have in common? This week’s podcast, of course! First up, I chat with Max Odendahl (CEO, Founder – Silexica) about ins and outs of system level understanding and optimization, what we can do with unsynthesizable C/C++ code and how we can tackle the biggest challenges in using Software (C/C++) for hardware … Read More → "Driving Optimization"
In part 1 of this series, we looked at new high-end FPGA families from Xilinx, Intel, and Achronix and discussed their underlying semiconductor processes, the type and amount of programmable logic LUT fabric, the type and amount of DSP/arithmetic resources and their applicability to AI inference acceleration tasks, the claimed TOPS/FLOPS performance capabilities, and on-chip interconnect … Read More → "High-End FPGA Showdown – Part 3"
Three decades ago – at the dawn of programmable logic technology – programmable logic devices such as CPLDs and FPGAs were primarily used for “glue logic.” That is, they could connect just about any digital thing to any other digital thing, regardless of the interface or protocol. In simple terms, FPGAs were digital duct tape.
Those times are long gone, however, with … Read More → "Lattice CrossLinkPlus"
The hot news on the street — if you live on a street where people build satellites and space probes for a hobby — is that those little scamps at Microchip Technology have just announced their new radiation-tolerant (RT) PolarFire FPGA, which they proudly proclaim, “…is optimized to meet the most demanding requirements in spacecraft payload systems’ … Read More → "To the Stars with Microchip’s New RT PolarFire FPGAs"