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Arrow reveals first Dev Board for Intel Agilex 5 FPGAs, with two more boards planned

Arrow has just launched a development board for Intel’s soon-to-be-produced Agilex 5 SoC FPGAs, and two more such boards wait in the wings. The Arrow AXE5-Eagle board sports one Intel Agilex 5 E-series SoC FPGA. Initially, these development boards will incorporate an engineering sample of the SoC FPGA with 656K logic elements (LEs), while production boards, available by the end of the first half of 2024, will incorporate … Read More → "Arrow reveals first Dev Board for Intel Agilex 5 FPGAs, with two more boards planned"

Goodbye SnapEDA (Sad Face) | Hello SnapMagic (Happy Face)

I still find it hard to believe that the first time generative artificial intelligence (GenAI) in the form of ChatGPT by OpenAI impinged itself on the public consciousness—including what I laughingly think of as my own consciousness (but only when I consciously think about it)—was only a year ago (give or take a few days) as I pen these words.

Wow! … Read More → "Goodbye SnapEDA (Sad Face) | Hello SnapMagic (Happy Face)"

AMD develops Virtex UltraScale+ FPGA with low-latency Ethernet for its Alveo UL3524 fintech accelerator card

AMD has announced an FPGA-based accelerator card with ultra-low-latency Ethernet ports, specifically designed for high-frequency financial trading. Like all such cards, the Alveo UL3524 accelerator card pairs an FPGA with several high-speed, low-latency Ethernet ports, which terminate in four QSFP-DD cages. Each QSFP-DD cage is driven by eight GTF … Read More → "AMD develops Virtex UltraScale+ FPGA with low-latency Ethernet for its Alveo UL3524 fintech accelerator card"

The Freedom to Innovate: Arteris and the Rise of RISC-V

The adoption of RISC-V is spreading. Versatility and “freedom to innovate” are powering the ecosystem. In this week’s Fish Fry podcast, Frank Schirrmeister from Arteris and I explore how to enable better architecture optimization, manage different protocols with ease, and reduce interconnect area plus power consumption with network-on-chip IP.  Also this week, I check out new … Read More → "The Freedom to Innovate: Arteris and the Rise of RISC-V"

Lattice announces CrossLinkU-NX FPGA with USB 3.2 to Unlock Video Applications

Lattice has marked some new territory in the low-end FPGA market with the CrossLinkU-NX FPGA. While AMD and Intel have signaled renewed interest in this market by previewing the future appearance of the low-end Spartan UltraScale+ and Agilex 3 families respectively, Lattice has been busy rolling out new members of its low-end CrossLink family. The latest addition, called the CrossLinkU-NX FPGA, specifically targets video applications for the … Read More → "Lattice announces CrossLinkU-NX FPGA with USB 3.2 to Unlock Video Applications"

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featured blogs
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chalk talks
Shift Left with Calibre — Siemens  In this episode of Chalk Talk, Amelia Dalton and David Abercrombie from Siemens investigate the details of Calibre’s shift-left strategy. They take a closer look at how the tools and techniques in this design tool suite can help reduce signoff iterations and time to tapeout while also increasing design quality. Click here for more … Read More → "Shift Left with Calibre — Siemens"
AI/ML System Architecture Connectivity Solutions — Samtec and Mouser Electronics  In this episode of Chalk Talk, Amelia Dalton and Matthew Burns from Samtec investigate a variety of crucial design considerations for AI and ML designs, the role that AI chipsets play in the development of these systems, and why the right connectivity solution can make all the difference when it comes to your machine … Read More → "AI/ML System Architecture Connectivity Solutions — Samtec and Mouser Electronics"
Intel AI Update — Intel and Mouser Electronics  In this episode of Chalk Talk, Amelia Dalton and Peter Tea from Intel explore how Intel is making AI implementation easier than ever before. They examine the typical workflows involved in artificial intelligence designs, the benefits that Intel’s scalable Xeon processor brings to AI projects, and how you can take advantage of the Intel … Read More → "Intel AI Update — Intel and Mouser Electronics"
One Year of Synopsys Cloud: Adoption, Enhancements and Evolution — Synopsys  The adoption of the cloud in the design automation industry has encouraged innovation across the entire semiconductor lifecycle. In this episode of Chalk Talk, Amelia Dalton chats with Vikram Bhatia from Synopsys about how Synopsys is redefining EDA in the Cloud with the industry’s first complete browser-based EDA-as-a-Service cloud platform. They explore the benefits … Read More → "One Year of Synopsys Cloud: Adoption, Enhancements and Evolution — Synopsys"
Automated Benchmark Tuning — Synopsys   Benchmarking is a great way to measure the performance of computing resources, but benchmark tuning can be a very complicated problem to solve. In this episode of Chalk Talk, Nozar Nozarian from Synopsys and Amelia Dalton investigate Synopsys’ Optimizer Studio that combines an evolution search algorithm with a powerful user interface that can … Read More → "Automated Benchmark Tuning — Synopsys"
Power Multiplexing with Discrete Components — Toshiba and Mouser Electronics  Power multiplexing is a vital design requirement for a variety of different applications today. In this episode of Chalk Talk, Amelia Dalton chats with Talayeh Saderi from Toshiba about what kind of power multiplex solution would be the best fit for your next design. They discuss five unique design considerations that we should think … Read More → "Power Multiplexing with Discrete Components — Toshiba and Mouser Electronics"