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Microchip’s New CoaXPress 2.0 Chips Speed Machine Vision

It’s funny how, when you keep on hearing stories about companies heading in one direction, the news that someone is going the other way makes you sit up and pay attention. It reminds me of that old saying: “‘Dog bites a man’ is not news; ‘Man bites a dog’ is news.”

In my case, for the past couple of years I’ve been talking with companies … Read More → "Microchip’s New CoaXPress 2.0 Chips Speed Machine Vision"

Punching Above Their Weight, Achronix Beats the Odds

We first met Achronix back in 2004 and have been following them constantly for sixteen years now. We’ve seen the company go from a founder-funded startup developing revolutionary asynchronous FPGAs in New York using technology licensed from Cornell – to an innovative, successful, mature, Silicon Valley fabless semiconductor and IP company giving the likes of Intel and Xilinx constant trouble in the programmable logic market and staking … Read More → "Punching Above Their Weight, Achronix Beats the Odds"

Handling Radiation in SRAM-Based FPGAs (Part 2)

As we discussed in Part 1 of this two-part mega-mini-series, radiation in its various forms has long been the bane of designers of electronic systems, and the effects of radiation become more insidious and pervasive as integrated circuit fabrication processes employ smaller and smaller structures.

We also introduced the concepts of electromagnetic radiation (EM … Read More → "Handling Radiation in SRAM-Based FPGAs (Part 2)"

Handling Radiation in SRAM-Based FPGAs (Part 1)

Radiation in its various forms has long been the bane of the designers of electronic systems. Unfortunately, the effects of radiation become more insidious and pervasive as integrated circuit fabrication processes employ smaller and smaller structures. The problem is most acute in the case of FPGAs, which also have their configuration cells to contend with. Happily, a new fabrication process can dispel radiation-induced FPGA woes.

More ( … Read More → "Handling Radiation in SRAM-Based FPGAs (Part 1)"

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chalk talks
Benefits of FPGAs & eFPGA IP in Futureproofing Compute Acceleration   In the quest to accelerate and optimize today’s computing challenges such as AI inference, our system designs have to be flexible above all else. At the confluence of speed and flexibility are today’s new FPGAs and e-FPGA IP. In this episode of Chalk Talk, Amelia Dalton chats with Mike Fitton from Achronix about … Read More → "Benefits of FPGAs & eFPGA IP in Futureproofing Compute Acceleration"
SLX FPGA: Accelerate the Journey from C/C++ to FPGA   High-level synthesis (HLS) brings incredible power to FPGA design. But harnessing the full power of HLS with FPGAs can be difficult even for the most experienced engineering teams. In this episode of Chalk Talk, Amelia Dalton chats with Jordon Inkeles of Silexica about using the SLX FPGA tool to truly harness the power … Read More → "SLX FPGA: Accelerate the Journey from C/C++ to FPGA"
Smart Embedded Vision with PolarFire FPGAs — Microchip and Mouser Electronics   In embedded vision applications, doing AI inference at the edge is often required in order to meet performance and latency demands. But, AI inference requires massive computing power, which can exceed our overall power budget. In this episode of Chalk Talk, Amelia Dalton talks to Avery Williams of Microchip about using FPGAs to … Read More → "Smart Embedded Vision with PolarFire FPGAs — Microchip and Mouser Electronics"
TensorFlow to RTL with High-Level Synthesis — Cadence Design Systems   Bridging the gap from the AI and data science world to the RTL and hardware design world can be challenging. High-level synthesis (HLS) can provide a mechanism to get from AI frameworks like TensorFlow into synthesizable RTL, enabling the development of high-performance inference architectures. In this episode of Chalk Talk, Amelia Dalton chats … Read More → "TensorFlow to RTL with High-Level Synthesis — Cadence Design Systems"
Mom, I Have a Digital Twin? Now You Tell Me? — Cadence Design Systems   Today, one engineer’s “system” is another engineer’s “component.” The complexity of system-level design has skyrocketed with the new wave of intelligent systems. In this world, optimizing electronic system designs requires digital twins, shifting left, virtual platforms, and emulation to sort everything out. In this episode of Chalk Talk, Amelia Dalton chats with Frank … Read More → "Mom, I Have a Digital Twin? Now You Tell Me? — Cadence Design Systems"
Introducing Google Coral — Google and Mouser Electronics   AI inference at the edge is exploding right now. Numerous designs that can’t use cloud processing for AI tasks need high-performance, low-power AI acceleration right in their embedded designs. Wouldn’t it be cool if those designs could have their own little Google TPU? In this episode of Chalk Talk, Amelia Dalton chats with … Read More → "Introducing Google Coral — Google and Mouser Electronics"