Arrow has just launched a development board for Intel’s soon-to-be-produced Agilex 5 SoC FPGAs, and two more such boards wait in the wings. The Arrow AXE5-Eagle board sports one Intel Agilex 5 E-series SoC FPGA. Initially, these development boards will incorporate an engineering sample of the SoC FPGA with 656K logic elements (LEs), while production boards, available by the end of the first half of 2024, will incorporate … Read More → "Arrow reveals first Dev Board for Intel Agilex 5 FPGAs, with two more boards planned"
I still find it hard to believe that the first time generative artificial intelligence (GenAI) in the form of ChatGPT by OpenAI impinged itself on the public consciousness—including what I laughingly think of as my own consciousness (but only when I consciously think about it)—was only a year ago (give or take a few days) as I pen these words.
My poor old noggin is currently spinning like a top. I was just chatting with Shakeel Peera, who is VP of Marketing, Strategy, and Business Operations for the FPGA business unit at Microchip Technology.
The first piece of intelligence that blew … Read More → "Microchip, PolarFire, and the Imperative of the Intelligent Edge"
AMD develops Virtex UltraScale+ FPGA with low-latency Ethernet for its Alveo UL3524 fintech accelerator card
AMD has announced an FPGA-based accelerator card with ultra-low-latency Ethernet ports, specifically designed for high-frequency financial trading. Like all such cards, the Alveo UL3524 accelerator card pairs an FPGA with several high-speed, low-latency Ethernet ports, which terminate in four QSFP-DD cages. Each QSFP-DD cage is driven by eight GTF … Read More → "AMD develops Virtex UltraScale+ FPGA with low-latency Ethernet for its Alveo UL3524 fintech accelerator card"
The adoption of RISC-V is spreading. Versatility and “freedom to innovate” are powering the ecosystem. In this week’s Fish Fry podcast, Frank Schirrmeister from Arteris and I explore how to enable better architecture optimization, manage different protocols with ease, and reduce interconnect area plus power consumption with network-on-chip IP. Also this week, I check out new … Read More → "The Freedom to Innovate: Arteris and the Rise of RISC-V"
Lattice has marked some new territory in the low-end FPGA market with the CrossLinkU-NX FPGA. While AMD and Intel have signaled renewed interest in this market by previewing the future appearance of the low-end Spartan UltraScale+ and Agilex 3 families respectively, Lattice has been busy rolling out new members of its low-end CrossLink family. The latest addition, called the CrossLinkU-NX FPGA, specifically targets video applications for the … Read More → "Lattice announces CrossLinkU-NX FPGA with USB 3.2 to Unlock Video Applications"