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Go Configure and Multiply

Speedcore Custom Blocks and efabless’ New Design Challenge Series

Where else can you go for not one but two electronic engineering interviews with two of the coolest executives in the biz? Yep, right here. First up, Robert Blake (Achronix – CEO) and I discuss the details of their Speedcore custom blocks, the issues surrounding the efficiency of computation in SoC design, and the benefits of FPGA acceleration core integration. Also this week, Mike Wishart (efabless – CEO) gives us all the info about their new design challenge series called “Go Configure”. Mike and I chat about the who, what, when, and how of this contest: what is involved, what kind of engineers should participate, and what motivated efabless to create this design contest.

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Links for November 11, 2017

More information about Achronix

Achronix Speedcore Custom Blocks Supercharge Data Acceleration Systems

More information about efabless

More information about The Go Configure Design Challenge Series

 

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Robert Blake, CEO – Achronix

Jack Harding, CEO – eSilicon

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Jeff Waters, VP and General Manager – Altera

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Zhihong Liu, Chairman and CEO – ProPlus Solutions

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Carl Alberty, Vice President – Cirrus Logic

Maximilian Odendahl, CEO — Silexica

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Sanjay Pillay, CEO — Austemper

Louis Parks, CEO – SecureRF

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