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More AI Moves into EDA

Mentor’s Calibre Goes for Higher Yield, Shorter TAT
by Bryon Moyer - August 12, 2019

Anyone who’s anyone has at least one AI angle working for them. Unwilling to settle for just one angle, Mentor Graphics discussed two angles at this summer’s DAC. As an EDA company, they have two specific opportunities to find value with AI. One is to improve the design tools they provide; the other is to create design tools specifically for AI designs. Very different … Read More → "More AI Moves into EDA"

From Chip to City and Back Again

5G, Edge Computing, and Multi-Physics Analysis
by Amelia Dalton - August 9, 2019

“Here’s your ticket pack your bag: time for jumpin’ overboard.
The transportation is here.
Close enough but not too far, Maybe you know where you are.” – Talking Heads

In this week’s episode of Fish Fry, we investigate the complexities of data processing in coming age of 5G. Wade Smith (ANSYS) joins us to discuss the challenges of 5G … Read More → "From Chip to City and Back Again"

To the Cloud, Alice!

Three Cloud-Computing Stories from DH2i, Excelfore, and eSilicon
by Bryon Moyer - August 5, 2019

It’s like Manifest Destiny all over again (hopefully without the dark side). There’s an inexorable move to the cloud for computing – and yet all the pieces aren’t in place yet to make it ridiculously easy to get secure cloud connections. So today we discuss three different stories about moving to the cloud. One is EDA-related; the others apply to automotive and the Internet … Read More → "To the Cloud, Alice!"

Seeing is Believing

Vision Processing with Tensilica Q7 DSP and the First Optogenetics-Based IC
by Amelia Dalton - August 2, 2019

What has SLAM done for you lately? If you are working on a vision processing application, quite a lot most likely! In this week’s episode of Fish Fry, we welcome Pulin Desai from Cadence Design Systems. Pulin and I chat about the trends driving the need for more vision processing, the current challenges associated with SLAM (simultaneous localization and mapping) and when he thinks it is best to … Read More → "Seeing is Believing"

Swimming in the SoC

In-chip Monitoring, Embedded Analytics, and IC Integrity Verification
by Amelia Dalton - July 26, 2019

In this week’s episode of Fish Fry, we are swimming in SoCs! Randy Fish (UltraSoC) joins us to discuss the deep waters of embedded analytics and AI platform debug. Ramsay Allen (Moortec) and I chat about the rising tide of advanced chip node designs and the benefits of in-chip monitoring IP. Finally, Rob van Blommestein (OneSpin) and sail through the choppy waters of IC verification. </ … Read More → "Swimming in the SoC"

Articles Archive →
industry news
August 7, 2019
Cadence and UMC Collaborate on Certification of Analog/Mixed-Signal Flow for 28HPC+ Process
August 5, 2019
Altium Gathers Industry Luminaries and Designers for 3rd Annual AltiumLive Summit
August 2, 2019
Accellera Announces Public Source Code Repository
August 1, 2019
Synopsys and Ponemon Release New Study Highlighting Software Security Practices and Challenges in the Financial Services Industry
July 23, 2019
Synopsys and Ixia, a Keysight Business, Announce Collaboration to Enable Scalable Networking SoC Validation Solution
July 22, 2019
Cadence Introduces Conformal Litmus to Deliver Fastest Path to Full-Chip Constraints and CDC Signoff
July 18, 2019
Cadence Delivers Portable Test and Stimulus Methodology and Library
July 16, 2019
The MOSIS Service Selects Synopsys’ IC Validator for Large-scale FinFET SoCs
July 15, 2019
SmartDV Adds DisplayPort 2.0 to its Portfolio of Verification IP
Synopsys Awarded DARPA ERI Contract Extension for Analog/Mixed-Signal Emulation Technology Innovation
July 12, 2019
IC Compiler II 2019 Extends Runtime and QoR Leadership with 2X Faster Throughput and 10% Lower Total Power
July 11, 2019
Cadence Digital Full Flow Achieves Certification for Samsung Foundry 5LPE Process Technology
July 2, 2019
SmartDV Adds New Verification IP to Support OpenCAPI Standard
July 1, 2019
Code Dx and AdaCore Partner to Provide an Ada Application Security Testing Toolsuite
ES Design West Opens July 9 with Exhibit Floor Showcasing Companies that Span Entire Electronic System Design Ecosystem
Cadence Announces First-to-Market DisplayPort 2.0 Verification IP
June 19, 2019
Riviera-PRO™ users to benefit from automatic UVM register generation plus the latest verification methodology libraries
June 17, 2019
Toshiba Selects Cadence Tensilica Vision P6 DSP as Image Recognition Processor for its Next-Generation ADAS Chip
June 10, 2019
Socionext Adopts the Cadence Full-Flow Digital and Signoff Tools for 7nm Designs
June 7, 2019
Cadence Introduces the Spectre X Simulator, a Massively Parallel Circuit Simulator Delivering Up to 10X Faster Simulation with the Same Golden Accuracy
Altium Releases Altium Designer 19.1 and Free Tool for Online Design Visualization
June 6, 2019
Faraday Adopts Synopsys SpyGlass Design Handoff Kit to Ensure High Design Quality
June 5, 2019
Deliver “smarter” faster: Mentor introduces new AI/ML toolkit, adds AI/ML power to Calibre tools to speed smarter IC innovation
June 4, 2019
Mentor sets new software scaling benchmark for Semiconductor Design Workload on Microsoft Azure
June 3, 2019
Cadence Expands Customer-Managed Cloud Options with New Cloud Passport Partner Program
News Archive →
featured blogs
Automotive Security in the World of Tomorrow - Part 2 of 2
Aug 22, 2019
If you missed the first part of this series, you can find it here . So: what does Green Hills propose we do? The issue of '€œsolving security'€ is, at its core, impossible'€”security can never be 100%... [[ Click on the title to access the full blog on the Cadence Com...
More from Cadence...
Testing the Effects of Humidity on Connectors
Aug 21, 2019
Many electronics experience a wide range of climates while in operation and storage. Because of this fact, connector humidity testing is used to determine the ability of a product to withstand elevated humidity and cycling temperatures. Humidity testing is conducted in combin...
More from Samtec, Inc....
chalk talks
Accelerating Physical Verification Productivity   Physical verification can take an enormous amount of time, and catching errors early in the process is the best way to avoid costly and time-consuming iterations. In this episode of Chalk Talk, Amelia Dalton chats with Christen Decoin of Synopsys about accelerating physical design productivity with tools and methods that can help catch … Read More → "Accelerating Physical Verification Productivity"
Tensilica HiFi DSP   Performing speech recognition at the edge, rather than sending data back to the cloud, is a major engineering challenge. You need significant processing power on a tiny energy budget, and often in a small form-factor. In this episode of Chalk Talk, Amelia Dalton chats with Gerard Andrews of Cadence Design Systems about the … Read More → "Tensilica HiFi DSP"
Introducing Cadence Cloud Portfolio  EDA in the cloud has finally arrived! Now, when you need access to large amounts of computing power to push your design through those critical stages, there is a secure, reliable, powerful cloud-based system that lets you scale your design tools to meet your actual needs. In this episode of Chalk Talk, Amelia Dalton … Read More → "Introducing Cadence Cloud Portfolio"
Introducing the Visual Verification Suite’s New HDL Creator  Finding errors in a complex HDL design can be a daunting task. And, most errors aren’t detected until late in the design flow. If we could catch our errors earlier, when we are initially writing the code, we could save enormous amounts of time in simulation, synthesis, and layout. In this episode of Chalk … Read More → "Introducing the Visual Verification Suite’s New HDL Creator"
Understanding Power-Aware SimulationConsidering power delivery and signal integrity separately can lead to suboptimal results in PCB design. Signal return paths can interact with power delivery networks in a number of ways, and power-aware analysis can help identify and correct problems before you build your prototype. In this episode of Chalk Talk, Amelia Dalton chats with Todd Westerhoff … Read More → "Understanding Power-Aware Simulation"
A New Advanced IC Packaging Battlefield  Today, advanced packaging technology has created a new battleground where 2.5D packaging and heterogeneous design drive constraints that span semiconductor, packaging, board, and even system-level design. In this episode of Chalk Talk, Amelia Dalton chats with John Park of Cadence Design Systems about new techniques and tools for advanced IC packaging design. Click here … Read More → "A New Advanced IC Packaging Battlefield"
Chalk Talk Archive →