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Who Chooses Components and Tools?

Before becoming professional engineers, most of us designed and built things as a hobby. It’s rare to find an engineer who jumped right into engineering school without at least some background of tinkering and experimenting. And, when we did those projects, we had full control. We could choose whatever part we wanted or needed. We didn’t have to deal with management, manufacturing, … Read More → "Who Chooses Components and Tools?"

Achronix Accelerates eFPGA

Perhaps when the most important problem is a nail, every solution starts to look like a hammer. With the ramping explosion in AI and machine learning, countless companies are trying to climb on the bandwagon, morphing and melding their existing technologies in an attempt to come up with a differentiated solution that will capture a meaningful share of this mind-boggling emerging opportunity. Everybody from EDA vendors to cloud data … Read More → "Achronix Accelerates eFPGA"

The Spirit of 42

What do Douglas Adams, PCB design, DRAM for cryptocurrency, and the fourth Industrial Revolution have in common? This week’s episode of Amelia’s Weekly Fish Fry, of course! First up, Greg Roberts (EMA Design Automation) brings us the goods on EMA’s new ebook called “The Hitchhiker’s Guide to PCB Design”. Next, Mark Greenberg (Cadence Design Systems) and I chat about using DRAM4 for artificial … Read More → "The Spirit of 42"

Racing to the End of Moore’s Law: The New World Semiconductor Order

There’s a new world order coming for the semiconductor industry, said A.B. Kahng. We’re racing to the end of Moore’s Law, and the race will now be won by sheer capex (capital expenditures) and size. Kahng, Professor of CSE and ECE at UC San Diego, was speaking at the < … Read More → "Racing to the End of Moore’s Law: The New World Semiconductor Order"

The Significance of Sparsity

What has sparsity done for you lately? In this episode of Fish Fry, we investigate the challenges that surround on-device artificial intelligence processing. Megha Daga (Cadence Design Systems) and I discuss the why the presence of zeroes is becoming more and more important in the development of neural networks and how sparsity can be used for bandwidth and compute reduction. In this week’s News You May Have Missed, … Read More → "The Significance of Sparsity"

Xilinx Scores Azure Acceleration Win

Xilinx scored a major win recently, with Microsoft’s Azure cloud group reportedly making a commitment to use Xilinx devices in something like half of their future Azure deployments. Until now, Azure has been solidly in the Intel PSG (Altera) camp for FPGA-based acceleration. Microsoft says that every Azure server for the past several years has been equipped with FPGAs, and, until now, those … Read More → "Xilinx Scores Azure Acceleration Win"

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featured blogs
Dec 16, 2018
https://youtu.be/izP9iUskcXQ Made at the Cadence Marketing Holiday Party (camera Sean) Monday: RISC-V: Real Products in Volume Tuesday: IEDM: All About Interconnect Wednesday: The Conway... [[ Click on the title to access the full blog on the Cadence Community site. ]]...
Dec 13, 2018
In November, we continued our mobile updates to the website, released a couple of new content experiences, and made placing sample requests even easier. Read more below on these and the rest of the major updates to Samtec.com for November 2018. Continued Improvements to our M...
Dec 12, 2018
The possibilities for IoT devices, much like the internet itself, are endless. But with all of those possibilities comes risks....
Nov 14, 2018
  People of a certain age, who mindfully lived through the early microcomputer revolution during the first half of the 1970s, know about Bill Godbout. He was that guy who sent out crudely photocopied parts catalogs for all kinds of electronic components, sold from a Quon...
chalk talks
A New Advanced IC Packaging Battlefield  Today, advanced packaging technology has created a new battleground where 2.5D packaging and heterogeneous design drive constraints that span semiconductor, packaging, board, and even system-level design. In this episode of Chalk Talk, Amelia Dalton chats with John Park of Cadence Design Systems about new techniques and tools for advanced IC packaging design. Click here … Read More → "A New Advanced IC Packaging Battlefield"
Shift Left for Fewer PCB Re-Spins   Design rule checking (DRC) is becoming more important with today’s complex PCB designs. With the complexity of today’s designs, the old ad-hoc methods just don’t cut it. In this episode of Chalk Talk, Amelia Dalton chats with Rory Riggs from Mentor about how Hyperlynx DRC can help get your next design out on … Read More → "Shift Left for Fewer PCB Re-Spins"
Scaling Up Vision and AI DSP Performance  For high-performance, low-power processing of AI and machine vision algorithms, latency can be critical. In this episode of Chalk Talk, Amelia Dalton chats with Pulin Desai from Cadence Design Systems about the using the new Vision Q6 processor core for embedded vision and AI applications. Click here for more information about Vision DSPs for … Read More → "Scaling Up Vision and AI DSP Performance"
Debug and Verify FPGA Algorithms with MATLAB and Simulink   Today’s FPGA designs require industrial-strength functional verification. The ad-hoc methods that worked with older, smaller FPGAs just don’t cut it anymore. In this episode of Chalk Talk, Amelia Dalton chats with Eric Cigan of MathWorks about ASIC-strength functional verification with model-based design. Click here for more information about how to verify VHDL and … Read More → "Debug and Verify FPGA Algorithms with MATLAB and Simulink"
Simulation-Based Tuning of Power Electronics Controllers   Power electronics are becoming more complex these days, and simulating your digital power controller gives significant advantages. In this episode of Chalk Talk, Amelia Dalton chats with Arkadiy Turevskiy of MathWorks about how to tune digital power electronics controllers with simulation. Click here for more information about Simulation-Based Tuning of Power Electronics Controllers.
Addressing Challenges with Large SerDes System Designs  The latest high-speed SerDes standards put high demands on PCB design. In this episode of Chalk Talk, Amelia Dalton chats with Cristian Filip of Mentor about best practices and tools you can apply to implementing and validating the SerDes design on your next circuit board. Click here for more information about SerDes Channel Design … Read More → "Addressing Challenges with Large SerDes System Designs"