When I worked on my first ASIC deep in the mists of time that we used to call the 1980s, we employed a traditional “waterfall” model for our design and verification flows. In this case, any activities associated with the project were broken down into linear sequential phases, where each phase depended on the deliverables from the previous one.
The … Read More → "Doing the Time Warp with Calibre DesignEnhancer"
As is usually the case, I’m astonished and astounded by the leaps in technology that are occurring all around me. Things are now moving so fast that there will probably be yet another mindboggling development before I’ve finished this column (so I’d better write it as quickly as I can).
The generation of electronics engineers that came before your humble … Read More → "Are You Ready for the Chiplet Age?"
If you want the world to celebrate and remember your life’s accomplishments, the best way to achieve that goal is to write an autobiographical book about your life. If you want to make sure that book is printed and distributed, then publish it yourself. That’s exactly what processor architect extraordinaire Pat Hays has done. He wrote and recently self-published “Read More → "Book Review: “Silicon Planet” describes the hands-on, hard-knocks education of a processor architect"
Two presentations during the same week from Intel and Movellus highlighted radically different approaches to solving voltage droop, a problem that increasingly plagues SoC designs as device geometries continue marching down the Moore’s Law curve. Intel, being a manufacturing-centric company, has developed a backside power distribution network (PDN) for its Intel 20A and 18A process nodes. Meanwhile, IP vendor Movellus has developed an extension to its … Read More → "Intel and Movellus Develop Different Fixes For IC Voltage Droop"
In this week’s podcast, my guest is DAC60 Engineering Tracks Program Chair Ambar Sarkar. Ambar and I chat all about this year’s Design Automation Conference including the new aspects of this year’s exhibition and conference, the RISC-V zone, what you can expect from this year’s visionary talks and keynotes, and the details of the DAC60 Celebration Panel called Designing the Future. Also this week, I … Read More → "Designing the Future: The Design Automation Conference Celebrates 60 Years!"
Physically aware network-on-chips take center stage in this week’s Fish Fry podcast! Andy Nightingale from Arteris and I investigate the role that network-on-chips have played in the development of SoC designs. We also discuss the details of Arteris’ FlexNoC 5 Physically Aware Network-on-Chip IP, and how a physically aware NoC can not only help you address your PPA goals but also get you to physical convergence faster. Also this … Read More → "The Network-on-Chip Pioneer: How Arteris Enabling SoC Developers to Create Physically Valid NoCs Faster"
