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No More Nanometers

“I learned how to measure before I knew what was size.” – Sofi Tukker, “House Arrest”

Let’s start by speaking some truth. Nothing about the “5 nanometer” CMOS process has any real relationship to five actual nanometers and transistor size. That train jumped off the rails years ago, and the semiconductor industry has inflicted tremendous self-harm by perpetuating the … Read More → "No More Nanometers"

Lattice Launches Certus-NX

Lattice Semiconductor has a knack for finding and exploiting holes in the programmable logic market. Years ago, they gave up chest beating their way into a distant third place in the FPGA market and decided instead to concentrate on the areas that the two dominant players (Xilinx and Intel/Altera) were ignoring. In a broad sense, that meant low-end FPGAs – devices with small form factors, small … Read More → "Lattice Launches Certus-NX"

TNG of DFT

Most people are familiar with the TNG concept, which sprang from the original Star Trek TV series being rebranded as “Star Trek: The Original Series” when its shiny successor “Star Trek: The Next Generation (TNG)” appeared on the scene (no pun intended). Well, I’ve just been introduced to the next generation (TNG) of design for test (DFT).

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A Google for Components

“The search for happiness is one of the chief sources of unhappiness.” — Eric Hoffer

It’s not often that you get to solve two problems at once. Or that one product serves two markets simultaneously. But that’s the clever business strategy behind a new search engine that helps PCB designers find component footprints while also giving component … Read More → "A Google for Components"

Debugging as a Career Goal

“There has never been an unexpectedly short debugging period in the history of computers.” – Steven Levy

Debugging your code or hardware is rarely seen as the glamorous part of the job. As engineers, we like to make stuff – to design. Any debugging activity is a tacit admission that our designs aren’t perfect; that we didn’t get … Read More → "Debugging as a Career Goal"

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featured blogs
Aug 7, 2020
HPC. FinTech. Machine Learning. Network Acceleration. These and many other emerging applications are stressing data center networks. Data center architectures evolve to ensure optimal resource utilization and allocation. PECFF (PCIe® Enclosure Compatible Form Factor) was dev...
Aug 6, 2020
Would you believe that the clever Victorians had incredibly cunning 21-segment incandescent lamp-based displays as far back as 1898?...
Aug 6, 2020
Rigid-flex sounds like something that might be a Crossfit workout-of-the-day. But it is actually a way of doing electronic design for small form factors using flexible PCBs (typically along with some... [[ Click on the title to access the full blog on the Cadence Community s...
Jul 31, 2020
[From the last episode: We looked at the notion of sparsity and how it helps with the math.] We saw before that there are three main elements in a CNN: the convolution, the pooling, and the activation . Today we focus on activation . I'€™ll start by saying that the uses of ...
chalk talks
Cloud Computing for Electronic Design (Are We There Yet?)   When your project is at crunch time, a shortage of server capacity can bring your schedule to a crawl. But, the rest of the year, having a bunch of extra servers sitting around idle can be extremely expensive. Cloud-based EDA lets you have exactly the compute resources you need, when you need them. … Read More → "Cloud Computing for Electronic Design (Are We There Yet?)"
SLX FPGA: Accelerate the Journey from C/C++ to FPGA   High-level synthesis (HLS) brings incredible power to FPGA design. But harnessing the full power of HLS with FPGAs can be difficult even for the most experienced engineering teams. In this episode of Chalk Talk, Amelia Dalton chats with Jordon Inkeles of Silexica about using the SLX FPGA tool to truly harness the power … Read More → "SLX FPGA: Accelerate the Journey from C/C++ to FPGA"
TensorFlow to RTL with High-Level Synthesis — Cadence Design Systems   Bridging the gap from the AI and data science world to the RTL and hardware design world can be challenging. High-level synthesis (HLS) can provide a mechanism to get from AI frameworks like TensorFlow into synthesizable RTL, enabling the development of high-performance inference architectures. In this episode of Chalk Talk, Amelia Dalton chats … Read More → "TensorFlow to RTL with High-Level Synthesis — Cadence Design Systems"
Cadence Celsius Thermal Solver — Cadence Design Systems   Electrical-thermal co-simulation can dramatically improve the system design process, allowing thermal design adaptation to be done much earlier. The Cadence Celsius Thermal Solver is a complete electrical-thermal co-simulation solution for the full hierarchy of electronic systems from ICs to physical enclosures. In this episode of Chalk Talk, Amelia Dalton chats with CT Kao … Read More → "Cadence Celsius Thermal Solver — Cadence Design Systems"
Mom, I Have a Digital Twin? Now You Tell Me? — Cadence Design Systems   Today, one engineer’s “system” is another engineer’s “component.” The complexity of system-level design has skyrocketed with the new wave of intelligent systems. In this world, optimizing electronic system designs requires digital twins, shifting left, virtual platforms, and emulation to sort everything out. In this episode of Chalk Talk, Amelia Dalton chats with Frank … Read More → "Mom, I Have a Digital Twin? Now You Tell Me? — Cadence Design Systems"
Addressing Digital Implementation Challenges with Innovative Machine Learning TechniquesMachine learning is revolutionizing our designs these days with impressive new capabilities. But, have you considered using machine learning to actually create better designs? In this episode of Chalk Talk, Amelia Dalton chats with Rod Metcalf of Cadence Design Systems about how Cadence is using machine learning to help us get more out of our … Read More → "Addressing Digital Implementation Challenges with Innovative Machine Learning Techniques"