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Can HLS Partitioning Speed Up Placement and Routing of FPGA Designs? Yes, Oh Yes!

FPGA place-and-route software goes too fast, said no one ever. In fact, FPGA vendors have spent considerable effort in making their design software run faster on multicore processors. A paper recently presented at the ACM’s FPGA 2022 conference titled “RapidStream: Parallel Physical Implementation of FPGA HLS Designs,” describes a very interesting approach to pushing HLS designs through FPGA design software running on multicore processors faster. The … Read More → "Can HLS Partitioning Speed Up Placement and Routing of FPGA Designs? Yes, Oh Yes!"

The Art of Predictability : How Axiomise is Making Formal Verification Mainstream

In this week’s Fish Fry podcast, Ashish Darbari (Founder and CEO at Axiomise) joins me to chat about the past, present and future of formal verification. Ashish and I explore the three pillars of formal verification, how the perception of formal verification as changed over the years, and why we are seeing the increased adoption of formal verification today. Also this week, I delve into the details of … Read More → "The Art of Predictability : How Axiomise is Making Formal Verification Mainstream"

Minding the SoC Verification Gap: How Breker’s TrekApps Solve Specific Common Verification Challenges

SoC verification takes center stage in this week’s podcast! Dave Kelf (CEO of Breker) joins us to discuss why coherency is crucial to system-level verification today, the details of Breker’s new TrekApps, and how these applications can help us bridge the SoC verification gap in our next SoC designs. Also this week, I take a closer look at how a new research project at University of Illinois … Read More → "Minding the SoC Verification Gap: How Breker’s TrekApps Solve Specific Common Verification Challenges"

Breaking Down Communication Barriers: How Altimade is Connecting Design, Supply Chain and Manufacturing

Are you designing with components that you cannot source? At what point in your design process do you think about manufacturing? This is exactly what we are exploring in this week’s Fish Fry podcast! Ted Pawela (Altium) joins me to discuss how Altium and MacroFab are addressing common PCB design communication and procurement issues with an industry-first integrated PCB “Design WITH Manufacturing” application called Altimade. Ted and I … Read More → "Breaking Down Communication Barriers: How Altimade is Connecting Design, Supply Chain and Manufacturing"

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featured blogs
May 25, 2022
Explore the world of point-of-care (POC) anatomical 3D printing and learn how our AI-enabled Simpleware software eliminates manual segmentation & landmarking. The post How Synopsys Point-of-Care 3D Printing Helps Clinicians and Patients appeared first on From Silicon To...
May 25, 2022
There are so many cool STEM (science, technology, engineering, and math) toys available these days, and I want them all!...
May 24, 2022
By Melika Roshandell Today's modern electronic designs require ever more functionality and performance to meet consumer demand. These requirements make scaling traditional, flat, 2D-ICs very... ...
May 24, 2022
By Neel Natekar Radio frequency (RF) circuitry is an essential component of many of the critical applications we now rely… ...
chalk talks
Enabling Digital Transformation in Electronic Design with Cadence Cloud — Cadence  With increasing design sizes, complexity of advanced nodes, and faster time to market requirements – design teams are looking for scalability, simplicity, flexibility and agility. In today’s Chalk Talk, Amelia Dalton chats with Mahesh Turaga from Cadence Design Systems about the details of Cadence’s end to end cloud portfolio, how you can extend your … Read More → "Enabling Digital Transformation in Electronic Design with Cadence Cloud — Cadence"
Faster, More Predictable Path to Multi-Chiplet Design Closure — Cadence Design Systems  The challenges for 3D IC design are greater than standard chip design – but they are not insurmountable. In this episode of Chalk Talk, Amelia Dalton chats with Vinay Patwardhan from Cadence Design Systems about the variety of challenges faced by 3D IC designers today and how Cadence’s integrated, high-capacity Integrity 3D IC Platform, … Read More → "Faster, More Predictable Path to Multi-Chiplet Design Closure — Cadence Design Systems"
Expanding SiliconMAX SLM to In-Field — Synopsys  In order to keep up with the rigorous pace of today’s electronic designs, we must have visibility into each step of our IC design lifecycle including debug, bring up and in-field operation. In this episode of Chalk Talk, Amelia Dalton chats with Steve Pateras from Synopsys about in-field infrastructure for silicon lifecycle management, the … Read More → "Expanding SiliconMAX SLM to In-Field — Synopsys"
10X Faster Analog Simulation with PrimeSim Continuum – Synopsys  IC design has come a very long way in a short amount of time. Today, our SoC designs frequently include integrated analog, 100+ Gigabit data rates and 3D stacked DRAM integrated into our SoCs on interposers. In order to keep our heads above water in all of this IC complexity, we need a unified … Read More → "10X Faster Analog Simulation with PrimeSim Continuum – Synopsys"
Solutions for Heterogeneous Multicore — Siemens   Multicore processing is more popular than ever before but how do we take advantage of this new kind of processing? In this episode of Chalk Talk, Jeff Hancock from Siemens and Amelia Dalton investigate the challenges inherent in multicore processing, the benefits of hypervisors and multicore frameworks, and what you need to consider … Read More → "Solutions for Heterogeneous Multicore — Siemens"
Machine-Learning Optimized Chip Design — Cadence Design Systems  New applications and technology are driving demand for even more compute and functionality in the devices we use every day. System on chip (SoC) designs are quickly migrating to new process nodes, and rapidly growing in size and complexity. In this episode of Chalk Talk, Amelia Dalton chats with Rod Metcalfe about how machine … Read More → "Machine-Learning Optimized Chip Design — Cadence Design Systems"