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Developing the World’s First Commercially Available RF Device with an Open-Source Chip

Good Grief! I can’t believe it’s 2023. I’m not ready. I haven’t got a speech prepared and I don’t have a thing to wear. I hope you had a wonderful holiday break with family and friends. For myself, I was originally hoping to take a 4-day weekend around Christmas Day followed by a repeat performance around New Year’s Eve.

< … Read More → "Developing the World’s First Commercially Available RF Device with an Open-Source Chip"

Introducing SafeConnect Connectivity and Glitch Sign-Off from Real Intent

Sometimes I cast my mind back longingly to my early days as a design engineer when things were so much simpler than they are now. When I was working on my first ASIC, there was no thought of using functional blocks of intellectual property (IP) from third-party vendors because there were no such things as functional blocks of IP from third-party vendors.

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Virtualize This! How Virtual Modeling will Change the Future of IoT Development

Longtime friend of the show Bill Neifert (Corellium) joins me this week to chat about the benefits virtual modeling can bring to the world of IoT. We discuss trends in IoT system design today and how Arm and Corellium are looking to transform IoT development and testing environments with virtualization technology.

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A Billion Instances and Counting – Solving the Challenges of IC Design Closure

Integrated circuits once again take center stage in this week’s Fish Fry podcast! Brandon Bautz (Cadence Design Systems) and I chat about the challenges of IC design closure today, how distribution and optimization can help address these growing design challenges, and the details of the Cadence® Certus™ Closure Solution. Also this week I investigate a new soft robot developed by Cornell University that can detect damage and heal … Read More → "A Billion Instances and Counting – Solving the Challenges of IC Design Closure"

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chalk talks
Automated Benchmark Tuning — Synopsys   Benchmarking is a great way to measure the performance of computing resources, but benchmark tuning can be a very complicated problem to solve. In this episode of Chalk Talk, Nozar Nozarian from Synopsys and Amelia Dalton investigate Synopsys’ Optimizer Studio that combines an evolution search algorithm with a powerful user interface that can … Read More → "Automated Benchmark Tuning — Synopsys"
Enabling Digital Transformation in Electronic Design with Cadence Cloud — Cadence  With increasing design sizes, complexity of advanced nodes, and faster time to market requirements – design teams are looking for scalability, simplicity, flexibility and agility. In today’s Chalk Talk, Amelia Dalton chats with Mahesh Turaga from Cadence Design Systems about the details of Cadence’s end to end cloud portfolio, how you can extend your … Read More → "Enabling Digital Transformation in Electronic Design with Cadence Cloud — Cadence"
Faster, More Predictable Path to Multi-Chiplet Design Closure — Cadence Design Systems  The challenges for 3D IC design are greater than standard chip design – but they are not insurmountable. In this episode of Chalk Talk, Amelia Dalton chats with Vinay Patwardhan from Cadence Design Systems about the variety of challenges faced by 3D IC designers today and how Cadence’s integrated, high-capacity Integrity 3D IC Platform, … Read More → "Faster, More Predictable Path to Multi-Chiplet Design Closure — Cadence Design Systems"
Expanding SiliconMAX SLM to In-Field — Synopsys  In order to keep up with the rigorous pace of today’s electronic designs, we must have visibility into each step of our IC design lifecycle including debug, bring up and in-field operation. In this episode of Chalk Talk, Amelia Dalton chats with Steve Pateras from Synopsys about in-field infrastructure for silicon lifecycle management, the … Read More → "Expanding SiliconMAX SLM to In-Field — Synopsys"
10X Faster Analog Simulation with PrimeSim Continuum – Synopsys  IC design has come a very long way in a short amount of time. Today, our SoC designs frequently include integrated analog, 100+ Gigabit data rates and 3D stacked DRAM integrated into our SoCs on interposers. In order to keep our heads above water in all of this IC complexity, we need a unified … Read More → "10X Faster Analog Simulation with PrimeSim Continuum – Synopsys"
Solutions for Heterogeneous Multicore — Siemens   Multicore processing is more popular than ever before but how do we take advantage of this new kind of processing? In this episode of Chalk Talk, Jeff Hancock from Siemens and Amelia Dalton investigate the challenges inherent in multicore processing, the benefits of hypervisors and multicore frameworks, and what you need to consider … Read More → "Solutions for Heterogeneous Multicore — Siemens"