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So Many Verification Cycles, So Little Time

Are you ready for an EDA smorgasbord? In this week’s episode of Fish Fry, we are laying out virtual buffet of emulation, hardware assisted development, enterprise prototyping, and parser platforms for your friday podcasting pleasure. First up, Frank Schirrmeister (Cadence Design Systems) joins us to dish about our growing thirst for verification, the benefits of FPGA based prototyping and why hardware-assisted development is more and more important these … Read More → "So Many Verification Cycles, So Little Time"

High-End FPGA Showdown – Part 3

In part 1 of this series, we looked at new high-end FPGA families from Xilinx, Intel, and Achronix and discussed their underlying semiconductor processes, the type and amount of programmable logic LUT fabric, the type and amount of DSP/arithmetic resources and their applicability to AI inference acceleration tasks, the claimed TOPS/FLOPS performance capabilities, and on-chip interconnect … Read More → "High-End FPGA Showdown – Part 3"

Plotting a Course to Functional Safety

There are many roads to prosperity, but one must be taken. Inaction leads nowhere. – Robert Zoellick

Security is not implemented overnight. Standards don’t create themselves. And our design lives won’t get easier if security and standards aren’t addressed at every step of the game. In this week’s podcast, Brent Sherman (Intel), Adam Sherer (Cadence) and I chat about the challenges of … Read More → "Plotting a Course to Functional Safety"

5G Meets 50,000 Fans at Super Bowl 2025

Recently, I was basking in my comfy command chair relishing the adverts on television. They’re really the only thing worth watching since the Gilmore Girls ended (my wife, Gina the Gorgeous, and I just finished watching the re-runs… again) and while one is waiting for the next season of Doctor Who starring Jodie Whittaker to launch in 2020.

One of these adverts showed a bunch of people … Read More → "5G Meets 50,000 Fans at Super Bowl 2025"

IP Market Large, Growing, and Strange

The semiconductor IP market is big, growing, lopsided, lumpy, and weird.

What it’s not is particularly lucrative. Which is odd, considering that you’re selling the rights to intangible goods and collecting royalties on that in perpetuity. At first blush, it’s like printing money, just without the money part.

The total IP market raked in somewhere around Read More → "IP Market Large, Growing, and Strange"

Up Up and Away

“I think everybody understands how important the cloud is.” – Marc Benioff

They say every cloud has a silver lining but does every silver lining have a cloud? In this week’s Fish Fry podcast, Craig Johnson (Cadence Design Systems) joins us to discuss a variety of cloud strategies. We investigate how priorities and usage models should influence our choice of cloud models and why different … Read More → "Up Up and Away"

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featured blogs
Dec 9, 2019
'Virtuoso Meets Maxwell' is a blog series aimed at exploring the capabilities and potential of Virtuoso® RF Solution and Virtuoso MultiTech. So, how does Virtuoso meets Maxwell? Now, the... [[ Click on the title to access the full blog on the Cadence Community...
Dec 6, 2019
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[From the last episode: We looked at the role of interrupts in a processor, and how they help save energy in battery-powered IoT devices.] OK, time to take a breath. We'€™ve covered a wide range of computing concepts; time for a quick review. We started by looking at the ro...
chalk talks
Prototyping Billion-Gate Designs with Protium X1 Enterprise Prototyping System   FPGA-based Prototyping certainly isn’t new. And our needs for early firmware and software development, memory modeling and advanced data capture haven’t gotten any better, if anything – they have gotten worse. Hi, I’m Amelia Dalton – host of Chalk Talk. Today my Juergen Jaeger from Cadence Design Systems and I are talking about … Read More → "Prototyping Billion-Gate Designs with Protium X1 Enterprise Prototyping System"
Accelerating Physical Verification Productivity   Physical verification can take an enormous amount of time, and catching errors early in the process is the best way to avoid costly and time-consuming iterations. In this episode of Chalk Talk, Amelia Dalton chats with Christen Decoin of Synopsys about accelerating physical design productivity with tools and methods that can help catch … Read More → "Accelerating Physical Verification Productivity"
Tensilica HiFi DSP   Performing speech recognition at the edge, rather than sending data back to the cloud, is a major engineering challenge. You need significant processing power on a tiny energy budget, and often in a small form-factor. In this episode of Chalk Talk, Amelia Dalton chats with Gerard Andrews of Cadence Design Systems about the … Read More → "Tensilica HiFi DSP"
Introducing Cadence Cloud Portfolio  EDA in the cloud has finally arrived! Now, when you need access to large amounts of computing power to push your design through those critical stages, there is a secure, reliable, powerful cloud-based system that lets you scale your design tools to meet your actual needs. In this episode of Chalk Talk, Amelia Dalton … Read More → "Introducing Cadence Cloud Portfolio"
Introducing the Visual Verification Suite’s New HDL Creator  Finding errors in a complex HDL design can be a daunting task. And, most errors aren’t detected until late in the design flow. If we could catch our errors earlier, when we are initially writing the code, we could save enormous amounts of time in simulation, synthesis, and layout. In this episode of Chalk … Read More → "Introducing the Visual Verification Suite’s New HDL Creator"
Understanding Power-Aware SimulationConsidering power delivery and signal integrity separately can lead to suboptimal results in PCB design. Signal return paths can interact with power delivery networks in a number of ways, and power-aware analysis can help identify and correct problems before you build your prototype. In this episode of Chalk Talk, Amelia Dalton chats with Todd Westerhoff … Read More → "Understanding Power-Aware Simulation"