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Doing the Time Warp with Calibre DesignEnhancer

When I worked on my first ASIC deep in the mists of time that we used to call the 1980s, we employed a traditional “waterfall” model for our design and verification flows. In this case, any activities associated with the project were broken down into linear sequential phases, where each phase depended on the deliverables from the previous one.

The … Read More → "Doing the Time Warp with Calibre DesignEnhancer"

Book Review: “Silicon Planet” describes the hands-on, hard-knocks education of a processor architect

If you want the world to celebrate and remember your life’s accomplishments, the best way to achieve that goal is to write an autobiographical book about your life. If you want to make sure that book is printed and distributed, then publish it yourself. That’s exactly what processor architect extraordinaire Pat Hays has done. He wrote and recently self-published “Read More → "Book Review: “Silicon Planet” describes the hands-on, hard-knocks education of a processor architect"

Intel and Movellus Develop Different Fixes For IC Voltage Droop

Two presentations during the same week from Intel and Movellus highlighted radically different approaches to solving voltage droop, a problem that increasingly plagues SoC designs as device geometries continue marching down the Moore’s Law curve. Intel, being a manufacturing-centric company, has developed a backside power distribution network (PDN) for its Intel 20A and 18A process nodes. Meanwhile, IP vendor Movellus has developed an extension to its … Read More → "Intel and Movellus Develop Different Fixes For IC Voltage Droop"

Designing the Future: The Design Automation Conference Celebrates 60 Years!

In this week’s podcast, my guest is DAC60 Engineering Tracks Program Chair Ambar Sarkar. Ambar and I chat all about this year’s Design Automation Conference including the new aspects of this year’s exhibition and conference, the RISC-V zone, what you can expect from this year’s visionary talks and keynotes, and the details of the DAC60 Celebration Panel called Designing the Future. Also this week, I … Read More → "Designing the Future: The Design Automation Conference Celebrates 60 Years!"

The Network-on-Chip Pioneer: How Arteris Enabling SoC Developers to Create Physically Valid NoCs Faster

Physically aware network-on-chips take center stage in this week’s Fish Fry podcast! Andy Nightingale from Arteris and I investigate the role that network-on-chips have played in the development of SoC designs. We also discuss the details of Arteris’ FlexNoC 5 Physically Aware Network-on-Chip IP, and how a physically aware NoC can not only help you address your PPA goals but also get you to physical convergence faster. Also this … Read More → "The Network-on-Chip Pioneer: How Arteris Enabling SoC Developers to Create Physically Valid NoCs Faster"

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featured blogs
Sep 28, 2023
See how we set (and meet) our GHG emission reduction goals with the help of the Science Based Targets initiative (SBTi) as we expand our sustainable energy use.The post Synopsys Smart Future: Our Climate Actions to Reduce Greenhouse Gas Emissions appeared first on Chip Des...
Sep 21, 2023
Not knowing all the stuff I don't know didn't come easy. I've had to read a lot of books to get where I am....
chalk talks
One Year of Synopsys Cloud: Adoption, Enhancements and Evolution — Synopsys  The adoption of the cloud in the design automation industry has encouraged innovation across the entire semiconductor lifecycle. In this episode of Chalk Talk, Amelia Dalton chats with Vikram Bhatia from Synopsys about how Synopsys is redefining EDA in the Cloud with the industry’s first complete browser-based EDA-as-a-Service cloud platform. They explore the benefits … Read More → "One Year of Synopsys Cloud: Adoption, Enhancements and Evolution — Synopsys"
Automated Benchmark Tuning — Synopsys   Benchmarking is a great way to measure the performance of computing resources, but benchmark tuning can be a very complicated problem to solve. In this episode of Chalk Talk, Nozar Nozarian from Synopsys and Amelia Dalton investigate Synopsys’ Optimizer Studio that combines an evolution search algorithm with a powerful user interface that can … Read More → "Automated Benchmark Tuning — Synopsys"
Enabling Digital Transformation in Electronic Design with Cadence Cloud — Cadence  With increasing design sizes, complexity of advanced nodes, and faster time to market requirements – design teams are looking for scalability, simplicity, flexibility and agility. In today’s Chalk Talk, Amelia Dalton chats with Mahesh Turaga from Cadence Design Systems about the details of Cadence’s end to end cloud portfolio, how you can extend your … Read More → "Enabling Digital Transformation in Electronic Design with Cadence Cloud — Cadence"
Faster, More Predictable Path to Multi-Chiplet Design Closure — Cadence Design Systems  The challenges for 3D IC design are greater than standard chip design – but they are not insurmountable. In this episode of Chalk Talk, Amelia Dalton chats with Vinay Patwardhan from Cadence Design Systems about the variety of challenges faced by 3D IC designers today and how Cadence’s integrated, high-capacity Integrity 3D IC Platform, … Read More → "Faster, More Predictable Path to Multi-Chiplet Design Closure — Cadence Design Systems"
Expanding SiliconMAX SLM to In-Field — Synopsys  In order to keep up with the rigorous pace of today’s electronic designs, we must have visibility into each step of our IC design lifecycle including debug, bring up and in-field operation. In this episode of Chalk Talk, Amelia Dalton chats with Steve Pateras from Synopsys about in-field infrastructure for silicon lifecycle management, the … Read More → "Expanding SiliconMAX SLM to In-Field — Synopsys"
10X Faster Analog Simulation with PrimeSim Continuum – Synopsys  IC design has come a very long way in a short amount of time. Today, our SoC designs frequently include integrated analog, 100+ Gigabit data rates and 3D stacked DRAM integrated into our SoCs on interposers. In order to keep our heads above water in all of this IC complexity, we need a unified … Read More → "10X Faster Analog Simulation with PrimeSim Continuum – Synopsys"