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IP Market Large, Growing, and Strange

Apart from One Big Winner, Fortunes are Decidedly Mixed
by Jim Turley - September 25, 2019

The semiconductor IP market is big, growing, lopsided, lumpy, and weird.

What it’s not is particularly lucrative. Which is odd, considering that you’re selling the rights to intangible goods and collecting royalties on that in perpetuity. At first blush, it’s like printing money, just without the money part.

The total IP market raked in somewhere around Read More → "IP Market Large, Growing, and Strange"

Up Up and Away

Different Clouds for Different Folks
by Amelia Dalton - September 13, 2019

“I think everybody understands how important the cloud is.” – Marc Benioff

They say every cloud has a silver lining but does every silver lining have a cloud? In this week’s Fish Fry podcast, Craig Johnson (Cadence Design Systems) joins us to discuss a variety of cloud strategies. We investigate how priorities and usage models should influence our choice of cloud models and why different … Read More → "Up Up and Away"

More AI Moves into EDA

Mentor’s Calibre Goes for Higher Yield, Shorter TAT
by Bryon Moyer - August 12, 2019

Anyone who’s anyone has at least one AI angle working for them. Unwilling to settle for just one angle, Mentor Graphics discussed two angles at this summer’s DAC. As an EDA company, they have two specific opportunities to find value with AI. One is to improve the design tools they provide; the other is to create design tools specifically for AI designs. Very different … Read More → "More AI Moves into EDA"

From Chip to City and Back Again

5G, Edge Computing, and Multi-Physics Analysis
by Amelia Dalton - August 9, 2019

“Here’s your ticket pack your bag: time for jumpin’ overboard.
The transportation is here.
Close enough but not too far, Maybe you know where you are.” – Talking Heads

In this week’s episode of Fish Fry, we investigate the complexities of data processing in coming age of 5G. Wade Smith (ANSYS) joins us to discuss the challenges of 5G … Read More → "From Chip to City and Back Again"

Articles Archive →
industry news
October 14, 2019
PROPHESEE Joins IRT Nanoelec 3D Integration Program
October 9, 2019
Synopsys Announces Industry-First Unified Functional Safety Verification Solution to Accelerate Time-to-Certification for IPs and SoCs
October 7, 2019
SmartDV Adds Support for Verilator Open Source HDL Verilog Simulator
October 4, 2019
Synopsys to Showcase Optimized Solutions for Arm-based Designs at Arm TechCon 2019
September 19, 2019
SmartDV Announces Availability of Ethernet TSN Design IP
September 18, 2019
Cadence Launches Celsius Thermal Solver, Delivering the Industry’s First Complete Electrical-Thermal Co-Simulation for System Analysis
September 16, 2019
Synopsys’ New Embedded Vision Processor IP Delivers Industry-Leading 35 TOPS Performance for Artificial Intelligence SoCs
September 12, 2019
Rockwell Automation helps businesses embrace the Fourth Industrial Revolution
September 10, 2019
Synopsys, Customers, and Partners Present the Latest Trends and Technologies in Embedded Processor Solutions at the Synopsys ARC Processor Summit
September 3, 2019
Synopsys Enables First-Pass Silicon Success of High Performance NSITEXE Data Flow Processor-based SoC Test Chip for Autonomous Driving
August 7, 2019
Cadence and UMC Collaborate on Certification of Analog/Mixed-Signal Flow for 28HPC+ Process
August 5, 2019
Altium Gathers Industry Luminaries and Designers for 3rd Annual AltiumLive Summit
August 2, 2019
Accellera Announces Public Source Code Repository
August 1, 2019
Synopsys and Ponemon Release New Study Highlighting Software Security Practices and Challenges in the Financial Services Industry
July 23, 2019
Synopsys and Ixia, a Keysight Business, Announce Collaboration to Enable Scalable Networking SoC Validation Solution
July 22, 2019
Cadence Introduces Conformal Litmus to Deliver Fastest Path to Full-Chip Constraints and CDC Signoff
July 18, 2019
Cadence Delivers Portable Test and Stimulus Methodology and Library
July 16, 2019
The MOSIS Service Selects Synopsys’ IC Validator for Large-scale FinFET SoCs
July 15, 2019
SmartDV Adds DisplayPort 2.0 to its Portfolio of Verification IP
Synopsys Awarded DARPA ERI Contract Extension for Analog/Mixed-Signal Emulation Technology Innovation
July 12, 2019
IC Compiler II 2019 Extends Runtime and QoR Leadership with 2X Faster Throughput and 10% Lower Total Power
July 11, 2019
Cadence Digital Full Flow Achieves Certification for Samsung Foundry 5LPE Process Technology
July 2, 2019
SmartDV Adds New Verification IP to Support OpenCAPI Standard
July 1, 2019
Code Dx and AdaCore Partner to Provide an Ada Application Security Testing Toolsuite
ES Design West Opens July 9 with Exhibit Floor Showcasing Companies that Span Entire Electronic System Design Ecosystem
News Archive →
featured blogs
Whiteboard Wednesdays – Verification with Emerging Memory Models
Oct 16, 2019
In this week's Whiteboard Wednesdays video, David Peña discusses Cadence'€™s focus on models for various emerging memory standards. https://youtu.be/_Xps6I6kE0E [[ Click on the title to access the full blog on the Cadence Community site. ]]...
More from Cadence...
Fundamentals: VR, MR, AR, DR, and HR
Oct 15, 2019
As technology advances, it's becoming harder and harder to know what is real and what isn't....
More from Max's Cool Beans...
Mixed criticality white paper
Oct 14, 2019
My working life includes a lot of writing – blogs, articles, conference papers and white papers are typical of what I produce. A common factor of my writing is that it is aimed to be technical and instructive. What I do not like writing is sales pitches. I can accept th...
More from Mentor...
Is Copper Dead?
Oct 14, 2019
In 1995, I attended a seminar in which the presenter told us that copper was dead.  This sort of statement is not new. The connector market is filled with armchair pundits who predict the demise of everything from D-Subminiature connectors (which are very much alive and ...
More from Samtec, Inc....
Cache on the Barrelhead
Oct 11, 2019
[From the last episode: We looked at subroutines in computer programs.] We saw a couple weeks ago that some memories are big, but slow (flash memory). Others are fast, but not so big '€“ and they'€™re power-hungry to boot (SRAM). This sets up an interesting problem. When ...
More from Inside the IoT...
chalk talks
Prototyping Billion-Gate Designs with Protium X1 Enterprise Prototyping System   FPGA-based Prototyping certainly isn’t new. And our needs for early firmware and software development, memory modeling and advanced data capture haven’t gotten any better, if anything – they have gotten worse. Hi, I’m Amelia Dalton – host of Chalk Talk. Today my Juergen Jaeger from Cadence Design Systems and I are talking about … Read More → "Prototyping Billion-Gate Designs with Protium X1 Enterprise Prototyping System"
Accelerating Physical Verification Productivity   Physical verification can take an enormous amount of time, and catching errors early in the process is the best way to avoid costly and time-consuming iterations. In this episode of Chalk Talk, Amelia Dalton chats with Christen Decoin of Synopsys about accelerating physical design productivity with tools and methods that can help catch … Read More → "Accelerating Physical Verification Productivity"
Tensilica HiFi DSP   Performing speech recognition at the edge, rather than sending data back to the cloud, is a major engineering challenge. You need significant processing power on a tiny energy budget, and often in a small form-factor. In this episode of Chalk Talk, Amelia Dalton chats with Gerard Andrews of Cadence Design Systems about the … Read More → "Tensilica HiFi DSP"
Introducing Cadence Cloud Portfolio  EDA in the cloud has finally arrived! Now, when you need access to large amounts of computing power to push your design through those critical stages, there is a secure, reliable, powerful cloud-based system that lets you scale your design tools to meet your actual needs. In this episode of Chalk Talk, Amelia Dalton … Read More → "Introducing Cadence Cloud Portfolio"
Introducing the Visual Verification Suite’s New HDL Creator  Finding errors in a complex HDL design can be a daunting task. And, most errors aren’t detected until late in the design flow. If we could catch our errors earlier, when we are initially writing the code, we could save enormous amounts of time in simulation, synthesis, and layout. In this episode of Chalk … Read More → "Introducing the Visual Verification Suite’s New HDL Creator"
Understanding Power-Aware SimulationConsidering power delivery and signal integrity separately can lead to suboptimal results in PCB design. Signal return paths can interact with power delivery networks in a number of ways, and power-aware analysis can help identify and correct problems before you build your prototype. In this episode of Chalk Talk, Amelia Dalton chats with Todd Westerhoff … Read More → "Understanding Power-Aware Simulation"
Chalk Talk Archive →