FPGA place-and-route software goes too fast, said no one ever. In fact, FPGA vendors have spent considerable effort in making their design software run faster on multicore processors. A paper recently presented at the ACM’s FPGA 2022 conference titled “RapidStream: Parallel Physical Implementation of FPGA HLS Designs,” describes a very interesting approach to pushing HLS designs through FPGA design software running on multicore processors faster. The … Read More → "Can HLS Partitioning Speed Up Placement and Routing of FPGA Designs? Yes, Oh Yes!"
In this week’s Fish Fry podcast, Ashish Darbari (Founder and CEO at Axiomise) joins me to chat about the past, present and future of formal verification. Ashish and I explore the three pillars of formal verification, how the perception of formal verification as changed over the years, and why we are seeing the increased adoption of formal verification today. Also this week, I delve into the details of … Read More → "The Art of Predictability : How Axiomise is Making Formal Verification Mainstream"
I am aghast, alarmed, astounded, shocked, and horrified. If pushed, I might admit to being flabbergasted (rarely has my flabber been so gasted). If I were feeling uncouth, I might even go so far as to say I was gobsmacked. How could something as awesome as what I am about to discuss have existed for so long without my knowing anything about it?
< … Read More → "You Too Can Rule the AoT with Audio Weaver"
