The Future of Human-Machine Interfaces

Intuition and HMI with eyeSight Technologies

by Amelia Dalton

Evolution is the name of the game in this week’s Fish Fry. The way we interact with our machines has changed dramatically in the past decade and will continue to evolve - from buttons and toggles to new, more hands-free forms of human-machine interface (HMI). I chat with Tal Krzypow from eyeSight Technologies about the future of HMI. We look at the growing trend toward hands-free interfaces, the important role intuition plays in the design of HMI, and where HMI is headed in the years to come. Also this week, we check out Element14’s new “DreamBoard vs Battle of the Boards” contest.  Read More

Industry News

May 29, 2015

System Level Power Workshop at DAC

New AdvancedTCA A/D Converter Blade from VadaTech Boasts 8 Channels at 2.6 GSPS

Xilinx Collaborates with TSMC on 7nm for Fourth Consecutive Generation of All Programmable Technology Leadership and Multi-node Scaling Advantage

IoT Subsystems from CAST and SoC Solutions Reduce Time to Market for Connected Products

µModule Regulator with Precision DC & Transient Output Regulation for Less than 28nm FPGAs Is Scalable up to 144A

Heart of Technology Hosts Love IP Party on June 8 at the Design Automation Conference

Mentor Graphics Veloce Power Application Redefines Power Analysis Flow

MEMSIC to Showcase its Latest Sensing Solutions at Sensors Expo and Conference 2015

Anritsu Introduces Universal USB Power Sensors with Best-in-Class Measurement Speed and Over-Power Protection Levels

May 28, 2015

Tekna launches a revolutionary material on the market : Boron Nitride NanoTubes

Cypress’s TrueTouch Touchscreen Controller Powers ZTE nubia Z7 Max Smartphone

sureCore Limited Brings Its First Ultra-Low Power SRAM IP To Market

Renesas Electronics Simplifies Sensor-less Brushless DC Motor Control Design for Home Appliance and Electric Power Tool Applications

PRO DESIGN Launches Complete Family of Virtex® UltraScale™ 440 FPGA Based Prototyping Systems

Semtech Launches New Low Dropout Regulator Platform for Small Form Factor Consumer Applications

May 27, 2015

OneSpin Solutions Catalyzes Unique, Third-Party Verification Solutions by Delivering OneSpin 360 LaunchPad, First Adaptive Formal Platform

Cypress Introduces High-Performance Synchronous SRAM Family With On-Chip Error-Correcting Code for Superior Reliability

QuickLogic Announces SenseMe Software Library Licensing for Smartphone, Wearable, and IoT Applications

New AMC from VadaTech Has 1.8” Quad SATA III SSD Module with RAID

Management Day at the 52nd DAC: The Impact of IoT and Big Data on Decision Making in EDA

Altium Releases New PCB Design Tool Engineered for SOLIDWORKS(r) Collaboration

May 26, 2015

4DSP Introduces Xilinx SDAccel Support and UltraScale FPGA Performance for Its Compact Embedded System

Vector Software Announces Enhanced Integration to Code Composer Studio™ IDE v6 from Texas Instruments®

STMicroelectronics Brings Smart Living to Consumers

Synopsys Expands Virtualizer Development Kit for Renesas RH850 with Support for RH850/P1x Series

Mentor Graphics Announces FloTHERM XT with EDA Connectivity for Advanced Thermal Management

IAR Systems leaves competition behind with unparalleled wide device support

Wideband 3GHz to 8GHz Mixer Improves Upconversion Performance with 25dBm OIP3 & 2dB Conversion Loss

News Archive

Bend it like Silicon

Flexible Silicon and Plastic Circuits

by Dick Selwood

Xilinx Loses Its Tail

The Next Evolutionary Step After FPGAs?

by Kevin Morris

Ignore Those Pesky Bugs

Software is Complicated, But How Much of it is Useful?

by Jim Turley

Portable Heterogeneous Multicore

The HSA Foundation’s New SoC Architecture

by Bryon Moyer

Articles Archive


Featured Video

editors' blog

Rumors Intel Altera Deal is Close

posted by Kevin Morris

The NY Post reported today that sources told them that an Intel/Altera deal was close, and could be done by the end of next week. At the same time, we are hearing from multiple Altera customers who are opposed to the deal. (28-May)

Is Exactly-Once Delivery Possible with MQTT?

posted by Bryon Moyer

If you’re trying to get a message sent and processed once and only once, can you rely on MQTT’s “exactly once” QoS setting? (28-May)

Differentiating Your IoT Widget – in Hardware

posted by Bryon Moyer

Open Silicon asserts that makers of IoT edge-node devices will need to differentiate in hardware in order to make money. (26-May)

Cadence’s Faster Debug Idea

posted by Bryon Moyer

Indago promises to allow debug without having to run verification multiple times to zero in on a bug. (19-May)

Faster NoC Tuning

posted by Bryon Moyer

Arteris says it has a way to get your NoC optimized faster than how you’ve been doing it. (12-May)

Editors' Blog Archive



Is Exactly-Once Delivery Possible with MQTT?

Posted on 05/28/15 at 4:01 PM by bmoyer

This is one of those topics that swirls in my head before, during, and after the time I'm writing. And, in that "after" time, I've changed my mind on something I said above. The thing about the sender setting a final state instead of an increment? I said …

Xilinx Loses Its Tail

Posted on 05/28/15 at 8:40 AM by Dick Selwood

Dick Selwood
The barrier for entry into the FPGA market has always been tools. If you talk to Altera/Xilin, you discover that they make a massive investment every year in tools. Anyone wanting to "just add some FPGA" to a SoC offering is going to have to develop a too…

Bend it like Silicon

Posted on 05/28/15 at 7:56 AM by Dick Selwood

Dick Selwood
What could you build with a flexible circuit?

Xilinx Loses Its Tail

Posted on 05/27/15 at 6:04 PM by kevin

I agree on most points. The (major) exception is that (from previous discussions) you and I have a dramatically different view on the complexity of industrial-strength software-to-gates technology. I don't think any of the companies you lis…

Xilinx Loses Its Tail

Posted on 05/27/15 at 6:04 PM by kevin

I agree on most points. The (major) exception is that (from previous discussions) you and I have a dramatically different view on the complexity of industrial-strength software-to-gates technology. I don't think any of the companies you lis…

Ignore Those Pesky Bugs

Posted on 05/27/15 at 3:16 PM by TotallyLost

I think it boils down to the necessary checks to bring up a new system without data corruption and memory faulting, vs what's necessary for safe operation after deployment.

A sane programmer is still using lot's of asserts at bring up ... to catch the …

Xilinx Loses Its Tail

Posted on 05/27/15 at 2:54 PM by TotallyLost

Good idea, except for the natural market problem the competition is Intel, AMD, Motorola, Freescale, Atmel, Microchip, and some two dozen other processor/SoC companies already in that market.

As soon as some major subset of those companies realize that…

Portable Heterogeneous Multicore

Posted on 05/27/15 at 2:35 PM by TotallyLost

In theory, once GPU's are integral to the CPU and share the cache bus interface, then OpenMP would allow the C/C++ compiler to use both resources transparently.

The bigger problem is also teaching the OS to context switch those resources as well .... s…

Xilinx Loses Its Tail

Posted on 05/27/15 at 11:21 AM by WEATHERBEE

Right Idea.

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Featured Chalk Talk

On Demand Archive

chalk talks

The Vault

Professional engineering projects require professional working practices. When we're designing things to be manufactured in volume, it's critical that we keep track of versions and revisions, collaborate and communicate effectively, and hand-off the right materials to manufacturing. In this episode of Chalk Talk, Amelia Dalton chats with Sam Sattel of Altium about Altium's "Vault" - which makes those professional practices a whole lot easier and smoother.

Vivado IP Flows

Doing IP-based design can be a major productivity booster for your engineering project. But, your ability to easily use and re-use IP can be severely limited if your design tools don't have robust support for creating the IP flow you want. In this episode of Chalk Talk, Amelia Dalton and Tim Vanevenhoven of Xilinx explain how you can create the perfect IP flow for your design process in the Vivado Design Suite from Xilinx.

Abstract and Conquer: A New Alternative to Hierarchical Timing Analysis

Sign-off timing analysis for today’s complex SoC designs can be daunting. Rather than just throwing more computer power at the problem, you need to adopt a hierarchical approach and take advantage of higher levels of abstraction. In this episode of Chalk Talk, Amelia Dalton talks with Ruben Molina of Cadence Design Systems about a new, faster approach to sign-off timing analysis.

Mixed Signal Verification: The Long and Winding Road

Verification of your mixed-signal design can be a nightmare, with clashing disciplines and engineering cultures, and challenging use-case requirements. In this episode of Chalk Talk, Amelia Dalton chats with Steve Carlson of Cadence Design Systems about a comprehensive approach to mixed-signal system verification.

FRAM Technology: The Next Generation of Non-volatile Memory for Microcontrollers

FRAM is one of the coolest non-volatile memory technologies to date. And, FRAM combined with microcontrollers is a perfect match. In this episode of Chalk Talk, Amelia Dalton chats with Will Cooper of Texas Instruments about the practical implications of FRAM technology in MCUs.

Increase FPGA Performance with Enhanced Capabilities of Synplify Pro & Premier

The most important factor in getting great performance from your FPGA design is optimization in synthesis and place and route. In this episode of Chalk Talk, Amelia Dalton chats with Paul Owens of Synopsys about the latest techniques for getting the most performance out of your design tools, and therefore out of your FPGA design.

Vivado IP Integrator

Even the best "plug and play" IP blocks are far from fool-proof. One of the most challenging aspects of IP-based design can be getting the blocks stitched together properly, making sure you have the right version of all the IP blocks, and confirming the configuration of your whole design. In this episode of Chalk Talk, Amelia Dalton chats with Tim Vanevenhoven about the powerful correct-by-construction automation built into the IP Integrator in Vivado Design Suite from Xilinx. IP Integrator seriously raises the bar on automation of IP-based design.

Chalk Talk Archive

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