What You Call EDA, I Call IP

EDA Past, Present, and Future with Lucio Lanza

by Amelia Dalton

He's toiled at this project for years - dreamt about it, laid awake at night thinking about it, and even built a lab in his basement to test it. Eventually he brought in friends (from work mostly) to fill in the missing pieces, and before he knew it they really had something. We all know this story. It has played out time and time again. It's the story of the startup, and today's Fish Fry celebrates the men and women who work every day with innovation in their hearts and minds. My distinguished guest is Lucio Lanza, an EDA mentor, venture capitalist, and believer in startup innovation. Lucio is here to explain why funding startups is so crucial in today's EE ecosystem and where he thinks EDA is headed in the future. Also this week, we check out a brand new way to get that semiconductor quote you've been looking for without giving you a headache or breaking your fax machine.  Read More


Industry News

December 19, 2014

Wearable Technology Products Demand Highly Accurate Biometric Technology

Pasternack Introduces New RF Combiners Operating Up to 6 GHz

Xilinx First to Move 20nm FPGAs into Volume Production

Nordic Semiconductor demonstrates IPv6 over Bluetooth Smart and hosts design partners' innovative wireless products at International CES 2015

Zuken Plays Key Role in Innovation Award Win for Electric Vehicle Research Collaboration

December 18, 2014

Real Intent Joins IEEE P2415™ Unified Hardware Abstraction and Layer Working Group

Cypress Introduces Industry’s Smallest USB 3.0 Hub Controller

Microchip Announces Qobuz Connect Support in JukeBlox® Platform

Nordic Semiconductor IPv6 over Bluetooth Smart protocol stack for nRF51 Series SoCs enables small, low cost, ultra-low power Internet of Things applications

Allegro MicroSystems, LLC Announces New Sensorless BLDC Controller

LED Driver from Diodes Offers High E-Transformer Compatibility in Non-Dimmable MR16 Lamp Design

Imec Presents Ultralow Power RFID Transponder Chip in Thin-Film Transistor Technology on Plastic at IEDM 2014

Econais Rolls Out New WiSmart EC19W01 Wi-Fi Software, Modules and Development Kits

December 17, 2014

Spansion and Sensoplex Launch High-Performance, Low-Power Wearable Development Platform

GLOBALFOUNDRIES and Cadence Deliver First SoC Enablement Solution Featuring ARM Cortex-A17 Processor in 28nm-SLP Process

PLDA ultra-compact System-on-Module Enables Lighthouse Imaging to Speed Up Design Turn-around for Image Acquisition and Processing

Industrial cybersecurity expert warns that not enough is being done to prevent risk of highly destructive cyberattack on critical infrastructure

IAR Systems reports major interest for integrated runtime analysis product

5A, 20VIN Step-Down µModule Regulator's Entire Solution Fits within 0.5cm²

Altium Announces Expanded Benefits to Subscription Customers

Synopsys' PrimeTime ADV Achieves Rapid Adoption for Fastest Timing Closure

New ASSET InterTech eBook explains how QPI self-healing bus can hinder circuit board quality

Semtech Partners with Link Labs On New Radio Module Featuring Long Distance LoRa™ Technology

December 16, 2014

Microsemi Announces Successful Completion of Nine NIST Cryptographic Algorithm Validation Program Certifications

Library Expert Enhanced Support for Altium Designer

Synopsys and Imec Expand TCAD Collaboration to 5 nm and Beyond

PNI Sensor’s Becky Oh Explores Getting to Low Power and Maximum Functionality through Sensor Fusion at 2015 CES

Imec Demonstrates Broadband Graphene Optical Modulator on Silicon

News Archive

electronica 2014

Fifty Years of Electronics in Munich

by Dick Selwood

I Am tRoot

Elliptic Technologies Delivers Hardware Root of Trust

by Jim Turley

Encapsulating Engineering

Construction at the End of the Road

by Kevin Morris

Five Ways to Detect

Different Approaches to Assessing the Environment

by Bryon Moyer

Articles Archive

 

EEJournal On The Scene Video News
 Hosted by Amelia Dalton

editors' blog

IoT Business Objects

posted by Bryon Moyer

Zatar, from Zebra, provides an interesting opportunity to examine yet another layer of the IoT. (18-Dec)

Beefed-Up Sensor Subsystem

posted by Bryon Moyer

Synopsys has updated the DesignWare subsystem that they debuted last year. (17-Dec)

The Power of the Pen

posted by Bryon Moyer

Studies suggest handwriting is important to brain development. Is typing putting us at risk? And are electronic pens up to the task? (16-Dec)

Sensor Algorithms Go Open Source

posted by Bryon Moyer

A new open-source collaboration for sensor algorithms was announced last month. (10-Dec)

Managing Context Options

posted by Bryon Moyer

Context awareness has incredible promise. But only if it gets things right without adding a new burden of teaching it how to get things right. (9-Dec)

Editors' Blog Archive

 

forum

I Am tRoot

Posted on 12/18/14 at 6:23 AM by RyanKenny

RyanKenny
Or 'Better Living Through Digital Signatures'

How to create mushroom designs on an oscilloscope signal detector using sound

Posted on 12/18/14 at 4:06 AM by HhindieR

Supply and demand go hand in hand. Where demand exists, supply will meet it. Some people demand they have dinosaur fossils, which leads to the interesting underworld of fossil smuggling. One of the more significant examples in recent memory is the case of…

Encapsulating Engineering

Posted on 12/18/14 at 1:29 AM by Kev

Not sure it's a good analogy (the "road" thing). The way we write software (C/C++) is very dependent on how the machines work, so there's a lot of interdependency that shouldn't be there in the "stack". The "top" of the current stack is reminding me of ho…

How to create mushroom designs on an oscilloscope signal detector using sound

Posted on 12/17/14 at 3:51 PM by EdB

Looks like the vector graphic displays of the 70s.

Five Ways to Detect

Posted on 12/15/14 at 9:31 AM by bmoyer

bmoyer
Will all these ways of detecting substances continue to coexist? Or do you see some winning or losing?

Berkeley’s RISC-V Wants to Be Free

Posted on 12/14/14 at 10:06 AM by Jim Turley

Jim Turley
I try to forget. wink

Managing Context Options

Posted on 12/12/14 at 10:02 PM by KevinAShaw

Completely agree. This will need to be done carefully. -Kevin

Berkeley’s RISC-V Wants to Be Free

Posted on 12/11/14 at 4:16 PM by MikeB

Aren't you forgetting SPICE. Far more useful (and brain-wrecking) than either LSD or Unix !!

New Synopsys SoC Test Features

Posted on 12/11/14 at 10:09 AM by bmoyer

bmoyer
What do you think about Synopsys's new test additions?

Forum Archive

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On Demand Archive

 Watch Chalk Talks
 On our New EE Journal YouTube Channel
 Hosted by Amelia Dalton

chalk talks

Enabling New Applications with NFC Connectivity and Energy Harvesting

In this episode of Chalk TalkHD Amelia chats with Greg Proehl (STMicroelectronics) about the basics of NFC technology, and they explore some interesting NFC applications as well as cool and innovative new NFC solutions from ST - including one with energy harvesting capability.

What is Electrically Aware Design?

For years, layout tools have focused on the pins and wires, the "froms" and "tos", the segments and nets - without considering that they were really creating a complex electrical circuit. Today, however, the electrical properties of our layout is critical, and issues like parasitic resistance and capacitance can have a dramatic effect on our final design. In this episode of Chalk Talk, Amelia Dalton chats with John Stabenow of Cadence about electrically-aware design with Cadence's Virtuoso.

Integrated Design Environment for FPGA

Do you find that FPGA design flows can get a bit confusing and difficult to manage? What we really need is an integrated design environment that will help us keep our design activities organized. In this episode of Chalk TalkHD Amelia chats with Satyam Jani from Aldec about integrated design environments (IDEs) for FPGA design, why FPGA designers need a vendor-independent IDE, and how an FPGA-centric IDE can help us get through our design flow quite a bit more easily.

Timing Closure Made Easier with Stylus

In this episode of Chalk TalkHD Amelia chats Andy Caldwell (Tabula) about putting an end to the oppressive reign of timing closure terror. Tabula’s Spacetime architecture - it turns out - besides giving us crazy performance for our high-bandwidth designs - also makes timing closure drop-dead easy.

High-Reliability in FPGA Design - SEU Mitigation

Neutrons are coming for you and you'd better be prepared. Whether we like it or not, SEUs (Single Event Upsets) are becoming a bigger and bigger problem for our designs, especially for high realibility systems. If you thought SEUs couldn't mess up your next design because you aren't designing something destined for space, you need to think again. In this episode of Chalk TalkHD, I chat with Jeff Garrison of Synopsys about the how we can battle SEUs (on the ground or in the air) with the latest generation of design tools.

High Speed Converters: What? Why? (and a little How?)

As we move our analog-to-digital conversion closer to the beginning of our signal chain, the performance demands can get extreme. In this episode of Chalk Talk, Amelia Dalton chats with David Robertson - VP at Analog Devices about how to design high-speed converters for today's most demanding applications.

Vivado IP Flows

Doing IP-based design can be a major productivity booster for your engineering project. But, your ability to easily use and re-use IP can be severely limited if your design tools don't have robust support for creating the IP flow you want. In this episode of Chalk Talk, Amelia Dalton and Tim Vanevenhoven of Xilinx explain how you can create the perfect IP flow for your design process in the Vivado Design Suite from Xilinx.

Chalk Talk Archive


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