Intel Plus Altera

What Would it Mean?

by Kevin Morris and Bruce Kleinman

There has been rampant speculation this week on rumors that Intel is in negotiations to buy Altera - in a deal that should be worth over ten billion, and which would be the largest acquisition in Intel’s history. While neither company is saying anything public yet, there is a substantial amount of information available from which to evaluate the potential impact of such a move and to speculate about the reasons behind it.

We actually predicted this eight months ago in our aptly-named article “When Intel Buys Altera” (subtle title, no?), and the arguments we made back then still apply today. But, with almost another year of progress under our collective belts, we should be able to raise the resolution on our crystal ball considerably. While there has been a considerable amount of press and analyst attention on these rumors, we think the analysts are largely off base. We’ll go into the problems with the analyst theories separately, but, for now, here is our take: 

Also - please note that there has not been any deal announced as of this writing. We are speculating here - caveat emptor.  Read More


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Rumors abound today that Intel is in negotiations to buy Altera - a deal that could be worth over ten billion. If so, it would be the largest acquisition in Intel's history. We have no confirmation from either company that such a deal is in play, but we did a pretty thorough analysis of the situation last June in this article: http://www.eejournal.com/archives/articles/20140624-intel/ What do you think? (27-Mar)

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forum

Intel Plus Altera

Posted on 03/31/15 at 12:21 PM by kleinman

kleinman
Doug-

You are spot-on, Intel's motivation is certainly multi-faceted. No doubt they see Altera's business as highly accretive to revenue, to say nothing of the gross margin dollar contribution.

Kevin and I chose to focus on the datacenter angle for …

Intel Plus Altera

Posted on 03/31/15 at 8:58 AM by dougafpga

Nice analysis, but I hope it's not that simple.
If Intel's alleged interest is a single-minded "hold the (data) centre", then what happens to all the other Altera users who suddenly find they are no longer at the focal point of a new "Intel FPGA division…

It’s EUV Season Again

Posted on 03/30/15 at 9:36 AM by bmoyer

bmoyer
Are you confident that EUV will materialize in a useful timeframe? Or are you making other plans?

A Low-Power Gyro – For Real

Posted on 03/28/15 at 9:42 PM by SteveNordquis4

SteveNordquis4
Cypress as in wacky currency and commodity leverage and high Russian representation, compliance seeks you; got it.

I thought we were going to have those UPS gyros (the ones with 70kg. shatter shields, yes) on exercise bands and make balance balls (thos…

Intel Buying Altera? We Totally Called It.

Posted on 03/28/15 at 7:25 AM by smithtronix

You deservedly should get credit for calling it last year. Of course it should not be a surprise as it really has been an excessively long time in coming. A chronology of technologies leading up to this marriage would be very interesting. Let's just hope …

When Intel Buys Altera

Posted on 03/27/15 at 11:10 PM by kevin

kevin
Well, this article seems to have suddenly taken on more relevance. What do you think?

We have just done an update on this topic with a new article:
"Intel Plus Altera - What Would it Mean?"
http://eejournal.com/archives/articles/20150331-intel/

TI MCU Goes 32-Bit

Posted on 03/25/15 at 9:31 PM by richw42

It's not obvious to me that the free MSPWare includes everything needed, such as a compiler. Why else would it be posed as a component of CCS?

HLS is the New Black

Posted on 03/25/15 at 11:57 AM by TotallyLost

TotallyLost
It's been nearly 20 years down this path, nice to see it realized productively with broad acceptance for large projects

It wasn't even 10 years ago while our team was doing FpgaC, that lead companies like Xilinx were openly rude and hostile to the con…

HLS is the New Black

Posted on 03/25/15 at 4:15 AM by dysonwilkes

Nice overview Kevin.

I often wonder if an HLS flow would be able to produce an implementation that has run-time flexibility. Maybe this is a system-level architecture issue: i.e. you compose sets of blocks implemented by HLS and orchestrate them with …

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