With the completion of the Azure Sky wind farm in Texas, we explore the impact of renewable energy, waste reduction, and more on our sustainability efforts.

Learn how virtual prototyping tools have replaced physical prototyping, reducing time-to-market by enabling pre-silicon software testing and code debugging.

We explain chiplets and share how Universal Chiplet Interconnect Express (UCIe) enables multi-die designs for SoC design innovation beyond Moore's Law.

We explain the multi-chip module packaging types & die-to-die interfaces helping chip designers create high-performance, multi-die designs in the SysMoore Era.

Explore our RIYA Returnship program, which helps professionals return to work after career breaks with 4-6 months of mentorship, reskilling, and networking.

Silicon lifecycle management (SLM) enables end-to-end visibility throughout the SoC design, manufacturing, and deployment process through intelligent analysis.

Autonomous vehicle safety and cybersecurity starts with automotive SoC design, protecting connected vehicles against data tampering and physical attacks.

We look at how AI and machine learning boost SoC verification, enhancing both static and formal verification and increasing chip simulation performance.

Learn how programmable SmartNICs enable homogeneous data center networking and storage architectures while taking the load off of primary compute resources.

See how cloud-based EDA tools and ready-to-use chip design flows accelerate the SoC design & verification process, thanks to Saas Instances on Synopsys Cloud.

Design Automation Conference (DAC) 2022 is almost here! Explore EDA and cloud design tools, autonomous systems, AI, and more with our experts in San Francisco.

In order to keep up with the rigorous pace of today’s electronic designs, we must have visibility into each step of our IC design lifecycle including debug, bring up and in-field operation. In this episode of Chalk Talk, Amelia Dalton chats with Steve Pateras from Synopsys about in-field infrastructure for silicon lifecycle management, the role that edge analytics play when it comes to in-field optimization, and how cloud analytics, runtime agents and SiliconMAX sensor analytics can provide you more information than ever before for the lifecycle of your IC design.

IC design has come a very long way in a short amount of time. Today, our SoC designs frequently include integrated analog, 100+ Gigabit data rates and 3D stacked DRAM integrated into our SoCs on interposers. In order to keep our heads above water in all of this IC complexity, we need a unified circuit simulation workflow and a fast signoff SPICE and FastSPICE architecture. In this episode of Chalk Talk, Amelia Dalton chats with Hany Elhak from Synopsys about how the unified workflow of the PrimeSim Continuum from Synopsys can help you address systematic and scale complexity for your next IC design.

Once a design goes to tape-out, the real challenges begin. Teams find themselves drowning in data from design-process-test during production ramp-up, and have to cope with data from numerous sources in different formats in the manufacturing test supply chain. In this episode of Chalk Talk, Amelia Dalton chats with Mark Laird of Synopsys in part three of our series on the Silicon LifeCycle Management (SLM) platform, discussing how Yield Explorer and SiliconDash give valuable insight to engineering and manufacturing teams.

In-chip monitoring can significantly alter the lifecycle management landscape. By taking advantage of modern techniques, today’s more complex designs can be optimized even after they are deployed. In this episode of Chalk Talk, Amelia Dalton chats with Stephen Crosher of Synopsys about silicon lifecycle management and how to take full advantage of the optimization opportunities available for scalability, reliability, and much more.

Wouldn’t it be great if we could keep on analyzing our IC designs once they are in the field? After all, simulation and lab measurements can never tell the whole story of how devices will behave in real-world use. In this episode of Chalk Talk, Amelia Dalton chats with Randy Fish of Synopsys about gaining better insight into IC designs through the use of embedded monitors and sensors, and how we can enable a range of new optimizations throughout the lifecycle of our designs.

Physical verification of IC designs at today’s advanced process nodes requires an immense amount of processing power. But, getting your design and verification tools to take full advantage of the compute resources available can be a challenge. In this episode of Chalk Talk, Amelia Dalton chats with Manoz Palaparthi of Synopsys about dramatically improving the performance of your physical verification process. 

Physical verification can take an enormous amount of time, and catching errors early in the process is the best way to avoid costly and time-consuming iterations. In this episode of Chalk Talk, Amelia Dalton chats with Christen Decoin of Synopsys about accelerating physical design productivity with tools and methods that can help catch errors earlier in the design process.

Learn how designers can take advantage of new ways to efficiently pinpoint voltage bottlenecks, drive voltage margin uniformity, and uncover opportunities to fine-tune operating voltages using PrimeShield design robustness solution.

What’s driving the need for a best-in-class solution for library characterization? In the latest Synopsys Designer’s Digest, learn about various SoC design challenges, requirements, and innovative technologies that deliver faster time-to-market with golden signoff quality. Learn how Synopsys’ PrimeLib™ solution addresses the increase in complexity and accuracy needs for advanced nodes and provides designers and foundries accelerated turn-around time and compute resource optimization.

See the Synopsys Multi-Protocol 112G PHY IP for long and medium reach interoperating with Amphenol's cable system, showing excellent BER and a path towards 224G connectivity.

In this edition of the Synopsys Aerospace and Defense Newsletter, Synopsys invites their partner, Ansys, to discuss joint solutions that help customers create systems with lower size, weight, and power (SWaP) through 3D heterogeneous integration (3DHI).

This OFC 2022 demo features Synopsys 112G Ethernet IP interoperating with AMD's 112G FPGA and 2.5m DAC, showcasing best TX and RX performance with auto negotiation and link training.

This OFC 2022 demo features the Synopsys 112G Ethernet IP directly equalizing electrical-optical-electrical (E-O-E) channel and supporting retimer-free CEI-112G linear drive for low-power applications.

This video features Synopsys USB4 PHY IP showing silicon correlation with IBIS-AMI simulation using Keysight PathWave ADS.

This DesignCon 2022 video features Synopsys PHY IP for PCIe 6.0 showing wide open PAM-4 eyes, good jitter breakdown decomposition on the Keysight oscilloscope, excellent receiver performance, and simulation-to-silicon correlation.

Performance-per-watt has emerged as one of the highest priorities in design quality, leading to a shift in technology focus and design power optimization methodologies. Variable operating voltage possess high potential in optimizing performance-per-watt results but requires a signoff accurate and efficient methodology to explore. Synopsys Fusion Design Platform™, uniquely built on a singular RTL-to-GDSII data model, delivers a full-flow voltage optimization and closure methodology to achieve the best performance-per-watt results for the most demanding semiconductor segments.

SLM presents significant value-driven opportunities for assessing the reliability and resilience of silicon devices, from data gathered during design, manufacture, test, and in-field. Silicon data driven analytics provide new actionable insights to address the challenges posed to large scale silicon designs.