See how we're harnessing generative AI throughout our suite of EDA tools with Synopsys.AI Copilot, the world's first GenAI capability for chip design.

Learn how integrating photonic integrated circuits (ICs) into multi-die systems via co-packaged optics increases bandwidth while reducing energy use.

We explain bluetooth low energy (BLE) technology, the benefits of combining BLE with other wireless protocols, and its impact on wireless SoC design.

We're advancing IC design talent and chip development in Vietnam through local training programs and collaboration with Vietnam's National Innovation Center.

We explain angstrom-scale chip design, exploring how it advances the semiconductor industry and how it improves SoC performance by extending Moore's Law.

Learn how cloud-based EDA tools automate software license management, accelerating the chip design flow by improving productivity and license scalability.

Two veterans of our digital marketing internship program explain how Synopsys interns make significant contributions to the company while learning valuable skills.

Learn how we're enhancing RISC-V design by expanding our ARC processor IP portfolio, as we introduce the open-source ARC-V instruction set architecture.

At Samsung SAFE Forum 2023 we explored how to accelerate analog circuit design migration to new process nodes with the help of artificial intelligence (AI).

Explore the past, present, and future of the RISC-V architecture, and learn about its performance advantages for HPC, AI, data centers, and automotive SoCs.

Learn how we're enabling interoperability for cloud EDA tools, allowing easy use of third-party chip design and verification tools in single cloud environment.

Learn how we're enhancing silicon photonics and data center infrastructure design through our work with OpenLight to accelerate optical system design.

The adoption of the cloud in the design automation industry has encouraged innovation across the entire semiconductor lifecycle. In this episode of Chalk Talk, Amelia Dalton chats with Vikram Bhatia from Synopsys about how Synopsys is redefining EDA in the Cloud with the industry’s first complete browser-based EDA-as-a-Service cloud platform. They explore the benefits that this on-demand pay-per use, web-based portal can bring to your next design. 

Benchmarking is a great way to measure the performance of computing resources, but benchmark tuning can be a very complicated problem to solve. In this episode of Chalk Talk, Nozar Nozarian from Synopsys and Amelia Dalton investigate Synopsys’ Optimizer Studio that combines an evolution search algorithm with a powerful user interface that can help you quickly setup and run benchmarking experiments with much less effort and time than ever before.

In order to keep up with the rigorous pace of today’s electronic designs, we must have visibility into each step of our IC design lifecycle including debug, bring up and in-field operation. In this episode of Chalk Talk, Amelia Dalton chats with Steve Pateras from Synopsys about in-field infrastructure for silicon lifecycle management, the role that edge analytics play when it comes to in-field optimization, and how cloud analytics, runtime agents and SiliconMAX sensor analytics can provide you more information than ever before for the lifecycle of your IC design.

IC design has come a very long way in a short amount of time. Today, our SoC designs frequently include integrated analog, 100+ Gigabit data rates and 3D stacked DRAM integrated into our SoCs on interposers. In order to keep our heads above water in all of this IC complexity, we need a unified circuit simulation workflow and a fast signoff SPICE and FastSPICE architecture. In this episode of Chalk Talk, Amelia Dalton chats with Hany Elhak from Synopsys about how the unified workflow of the PrimeSim Continuum from Synopsys can help you address systematic and scale complexity for your next IC design.

Once a design goes to tape-out, the real challenges begin. Teams find themselves drowning in data from design-process-test during production ramp-up, and have to cope with data from numerous sources in different formats in the manufacturing test supply chain. In this episode of Chalk Talk, Amelia Dalton chats with Mark Laird of Synopsys in part three of our series on the Silicon LifeCycle Management (SLM) platform, discussing how Yield Explorer and SiliconDash give valuable insight to engineering and manufacturing teams.

In-chip monitoring can significantly alter the lifecycle management landscape. By taking advantage of modern techniques, today’s more complex designs can be optimized even after they are deployed. In this episode of Chalk Talk, Amelia Dalton chats with Stephen Crosher of Synopsys about silicon lifecycle management and how to take full advantage of the optimization opportunities available for scalability, reliability, and much more.

Wouldn’t it be great if we could keep on analyzing our IC designs once they are in the field? After all, simulation and lab measurements can never tell the whole story of how devices will behave in real-world use. In this episode of Chalk Talk, Amelia Dalton chats with Randy Fish of Synopsys about gaining better insight into IC designs through the use of embedded monitors and sensors, and how we can enable a range of new optimizations throughout the lifecycle of our designs.

Physical verification of IC designs at today’s advanced process nodes requires an immense amount of processing power. But, getting your design and verification tools to take full advantage of the compute resources available can be a challenge. In this episode of Chalk Talk, Amelia Dalton chats with Manoz Palaparthi of Synopsys about dramatically improving the performance of your physical verification process. 

Adding safety measures to SoC designs in the form of radiation-hardened elements or redundancy is essential in making mission-critical applications in the A&D, cloud, automotive, robotics, medical, and IoT industries more resilient against random hardware failures that occur. This paper discusses the automated process of implementing the safety mechanisms/measures (SM) in the design to make them more resilient and analyze their effectiveness from design inception to the final product.

Learn how designers can take advantage of new ways to efficiently pinpoint voltage bottlenecks, drive voltage margin uniformity, and uncover opportunities to fine-tune operating voltages using PrimeShield design robustness solution.

What’s driving the need for a best-in-class solution for library characterization? In the latest Synopsys Designer’s Digest, learn about various SoC design challenges, requirements, and innovative technologies that deliver faster time-to-market with golden signoff quality. Learn how Synopsys’ PrimeLib™ solution addresses the increase in complexity and accuracy needs for advanced nodes and provides designers and foundries accelerated turn-around time and compute resource optimization.

Join Gary Ruggles, Synopsys Product Manager for PCIe & CXL, at PCI-SIG DevCon 2023 and see Synopsys PCIe 6.0 Controller & PHY IP in an end-to-end host to device system, using Teledyne LeCroy's interposer & analyzer showing impact of payload size on throughput.

See successful PCIe 6.0 interoperability demos in our booth & our partners’ booths at PCI-SIG DevCon 2023. Don’t miss our demo at 128 GT/s as we take a peek into the PCIe 7.0 tech and make sure to watch the world’s first PCIe 6.0 RX link training compliance tests.

At TSMC Symposium 2023 we showcased a successful 224G Ethernet PHY IP interop demonstration with backplane channels. Watch the various plots, ADC histogram and excellent eye diagrams results.

Watch this video of Synopsys 224G Ethernet PHY IP demonstrating wide-open TX PAM-4 eyes using Keysight’s oscilloscope & Samtec’s cables and connectors.

As glitch power becomes a growing component of total power, managing it requires a holistic solution for analysis and optimization from architecture to signoff. Watch this video and learn how to minimize glitch power in your designs.

This video shows how IC Compiler II and Fusion Compiler enable intelligent planning and implementation of complex interconnects through innovative Topological Interconnect Planning technology - accelerating schedules and achieving highest QoR.

The growing complexity of power management in chips requires a holistic approach to UPF power-intent generation and low power verification. Learn how Synopsys addresses these requirements with a comprehensive solution for low-power verification.

Watch this video of the Synopsys 224G & 112G Ethernet PHY IP demonstrating excellent performance and IP successful ecosystem interoperability demonstrations at OIF.