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Self-driving cars. Machines that learn. Lightning-fast communication across billions of devices in the datasphere. Synopsys technology is at the heart of innovations that are changing the way people work and play in our era of Smart Everything. We provide the world’s most advanced technologies for chip design, verification, IP integration, and software security and quality testing. In short, we help our customers innovate from silicon to software so they can bring Smart Everything to life.

 

From Silicon to Software

A Change in the Wind: Synopsys’ Sustainability Efforts Grow with a Wind Farm in Texas

With the completion of the Azure Sky wind farm in Texas, we explore the impact of renewable energy, waste reduction, and more on our sustainability efforts.

Aug 3, 2022
How Virtual Prototyping Tools Fast-Track Software Innovation and Time-to-Market

Learn how virtual prototyping tools have replaced physical prototyping, reducing time-to-market by enabling pre-silicon software testing and code debugging.

Aug 2, 2022
UCIe Heralds a Robust Chiplet Ecosystem for a New Era of SoC Innovation

We explain chiplets and share how Universal Chiplet Interconnect Express (UCIe) enables multi-die designs for SoC design innovation beyond Moore's Law.

Aug 1, 2022
A Primer on Chip Packaging for Multi-Die Designs

We explain the multi-chip module packaging types & die-to-die interfaces helping chip designers create high-performance, multi-die designs in the SysMoore Era.

Jul 27, 2022
Returning to Work After a Career Break Just Got Easier

Explore our RIYA Returnship program, which helps professionals return to work after career breaks with 4-6 months of mentorship, reskilling, and networking.

Jul 26, 2022
Silicon Lifecycle Management: Enabling Silicon Visibility Through Intelligent Analysis

Silicon lifecycle management (SLM) enables end-to-end visibility throughout the SoC design, manufacturing, and deployment process through intelligent analysis.

Jul 20, 2022
Achieving Greater Safety for Tomorrow’s Autonomous Vehicles

Autonomous vehicle safety and cybersecurity starts with automotive SoC design, protecting connected vehicles against data tampering and physical attacks.

Jul 19, 2022
AI: The Next Chapter in the Evolution of Verification

We look at how AI and machine learning boost SoC verification, enhancing both static and formal verification and increasing chip simulation performance.

Jul 13, 2022
How Can SmartNICs Move Your Data Center Forward?

Learn how programmable SmartNICs enable homogeneous data center networking and storage architectures while taking the load off of primary compute resources.

Jul 12, 2022
Synopsys Cloud SaaS Instances: Faster Time-to-Market for Higher Quality Chips

See how cloud-based EDA tools and ready-to-use chip design flows accelerate the SoC design & verification process, thanks to Saas Instances on Synopsys Cloud.

Jul 11, 2022
DAC 2022: A Glimpse into the World of Design Automation from the Cloud to Cryogenic Computing

Design Automation Conference (DAC) 2022 is almost here! Explore EDA and cloud design tools, autonomous systems, AI, and more with our experts in San Francisco.

Jul 6, 2022

Read more from the Synopsys Silicon to Software blog…

 

Chalk Talks Featuring Synopsys

Expanding SiliconMAX SLM to In-Field
In order to keep up with the rigorous pace of today’s electronic designs, we must have visibility into each step of our IC design lifecycle including debug, bring up and in-field operation. In this episode of Chalk Talk, Amelia Dalton chats with Steve Pateras from Synopsys about in-field infrastructure for silicon lifecycle management, the role that edge analytics play when it comes to in-field optimization, and how cloud analytics, runtime agents and SiliconMAX sensor analytics can provide you more information than ever before for the lifecycle of your IC design.
Jan 24, 2022
25,857 views
10X Faster Analog Simulation with PrimeSim Continuum
IC design has come a very long way in a short amount of time. Today, our SoC designs frequently include integrated analog, 100+ Gigabit data rates and 3D stacked DRAM integrated into our SoCs on interposers. In order to keep our heads above water in all of this IC complexity, we need a unified circuit simulation workflow and a fast signoff SPICE and FastSPICE architecture. In this episode of Chalk Talk, Amelia Dalton chats with Hany Elhak from Synopsys about how the unified workflow of the PrimeSim Continuum from Synopsys can help you address systematic and scale complexity for your next IC design.
Nov 1, 2021
34,076 views
Yield Explorer and SiliconDash
Once a design goes to tape-out, the real challenges begin. Teams find themselves drowning in data from design-process-test during production ramp-up, and have to cope with data from numerous sources in different formats in the manufacturing test supply chain. In this episode of Chalk Talk, Amelia Dalton chats with Mark Laird of Synopsys in part three of our series on the Silicon LifeCycle Management (SLM) platform, discussing how Yield Explorer and SiliconDash give valuable insight to engineering and manufacturing teams.
Apr 12, 2021
42,418 views
In-Chip Sensing and PVT Monitoring
In-chip monitoring can significantly alter the lifecycle management landscape. By taking advantage of modern techniques, today’s more complex designs can be optimized even after they are deployed. In this episode of Chalk Talk, Amelia Dalton chats with Stephen Crosher of Synopsys about silicon lifecycle management and how to take full advantage of the optimization opportunities available for scalability, reliability, and much more.
Mar 19, 2021
41,914 views
Silicon Lifecycle Management (SLM)
Wouldn’t it be great if we could keep on analyzing our IC designs once they are in the field? After all, simulation and lab measurements can never tell the whole story of how devices will behave in real-world use. In this episode of Chalk Talk, Amelia Dalton chats with Randy Fish of Synopsys about gaining better insight into IC designs through the use of embedded monitors and sensors, and how we can enable a range of new optimizations throughout the lifecycle of our designs.
Feb 25, 2021
42,075 views
Accelerating Physical Verification Productivity Part Two
Physical verification of IC designs at today’s advanced process nodes requires an immense amount of processing power. But, getting your design and verification tools to take full advantage of the compute resources available can be a challenge. In this episode of Chalk Talk, Amelia Dalton chats with Manoz Palaparthi of Synopsys about dramatically improving the performance of your physical verification process. 
Jan 27, 2021
40,323 views
Accelerating Physical Verification Productivity
Physical verification can take an enormous amount of time, and catching errors early in the process is the best way to avoid costly and time-consuming iterations. In this episode of Chalk Talk, Amelia Dalton chats with Christen Decoin of Synopsys about accelerating physical design productivity with tools and methods that can help catch errors earlier in the design process.
May 29, 2019
53,634 views

 

Synopsys Designer’s Digest

Improving Design Robustness and Efficiency for Today’s Advanced Nodes
Learn how designers can take advantage of new ways to efficiently pinpoint voltage bottlenecks, drive voltage margin uniformity, and uncover opportunities to fine-tune operating voltages using PrimeShield design robustness solution.
Sep 28, 2021
PrimeLib Next-Gen Library Characterization - Providing Accelerated Access to Advanced Process Nodes
What’s driving the need for a best-in-class solution for library characterization? In the latest Synopsys Designer’s Digest, learn about various SoC design challenges, requirements, and innovative technologies that deliver faster time-to-market with golden signoff quality. Learn how Synopsys’ PrimeLib™ solution addresses the increase in complexity and accuracy needs for advanced nodes and provides designers and foundries accelerated turn-around time and compute resource optimization.
Jul 14, 2021

 

Featured Videos from Synopsys

Synopsys 112G Multi-Protocol PHY IP and Amphenol 2m DAC & Examax Interoperability
See the Synopsys Multi-Protocol 112G PHY IP for long and medium reach interoperating with Amphenol's cable system, showing excellent BER and a path towards 224G connectivity.
Jul 19, 2022
16,369 views
Reduce SWaP with Multi-physics Aware 3D Heterogeneous Package Design
In this edition of the Synopsys Aerospace and Defense Newsletter, Synopsys invites their partner, Ansys, to discuss joint solutions that help customers create systems with lower size, weight, and power (SWaP) through 3D heterogeneous integration (3DHI).
Jul 12, 2022
21,871 views
Multi-Vendor Extra Long Reach 112G SerDes Interoperability Between Synopsys and AMD
This OFC 2022 demo features Synopsys 112G Ethernet IP interoperating with AMD's 112G FPGA and 2.5m DAC, showcasing best TX and RX performance with auto negotiation and link training.
Jun 24, 2022
23,949 views
Synopsys 112G Ethernet IP Interoperating with Optical Components & Equalizing E-O-E Link
This OFC 2022 demo features the Synopsys 112G Ethernet IP directly equalizing electrical-optical-electrical (E-O-E) channel and supporting retimer-free CEI-112G linear drive for low-power applications.
Jun 23, 2022
24,851 views
Synopsys USB4 PHY Silicon Correlation with Keysight ADS Simulation
This video features Synopsys USB4 PHY IP showing silicon correlation with IBIS-AMI simulation using Keysight PathWave ADS.
Jun 21, 2022
24,872 views
Synopsys PCIe 6.0 IP TX and RX Successful Interoperability with Keysight
This DesignCon 2022 video features Synopsys PHY IP for PCIe 6.0 showing wide open PAM-4 eyes, good jitter breakdown decomposition on the Keysight oscilloscope, excellent receiver performance, and simulation-to-silicon correlation.
Jun 15, 2022
24,798 views
Synopsys PPA(V) Voltage Optimization
Performance-per-watt has emerged as one of the highest priorities in design quality, leading to a shift in technology focus and design power optimization methodologies. Variable operating voltage possess high potential in optimizing performance-per-watt results but requires a signoff accurate and efficient methodology to explore. Synopsys Fusion Design Platform™, uniquely built on a singular RTL-to-GDSII data model, delivers a full-flow voltage optimization and closure methodology to achieve the best performance-per-watt results for the most demanding semiconductor segments.
May 10, 2022
25,454 views
Increasing Semiconductor Predictability in an Unpredictable World
SLM presents significant value-driven opportunities for assessing the reliability and resilience of silicon devices, from data gathered during design, manufacture, test, and in-field. Silicon data driven analytics provide new actionable insights to address the challenges posed to large scale silicon designs.
May 3, 2022
25,847 views