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Self-driving cars. Machines that learn. Lightning-fast communication across billions of devices in the datasphere. Synopsys technology is at the heart of innovations that are changing the way people work and play in our era of Smart Everything. We provide the world’s most advanced technologies for chip design, verification, IP integration, and software security and quality testing. In short, we help our customers innovate from silicon to software so they can bring Smart Everything to life.

 

New Horizons for Chip Design

Synopsys Bold Prediction: AI Will Begin Collaborating with AI in 2025

We predict the future of AI in 2025, including the development of AI agents, horizontal AI collaboration, and refinements in AI transparency across workloads.

Dec 12, 2024
Enabling Massive AI Clusters with the Industry’s First Ultra Ethernet and UALink IP Solutions

We explain why Ultra Ethernet and Ultra Accelerator Link (UALink) are critical to the expansion of AI infrastructure as AI HPC clusters scale both up and out.

Dec 11, 2024
Collaboration for Innovation: How Synopsys and TSMC are Advancing Chip Design

We're enhancing multi-die chip design with TSMC, using AI-driven EDA tools, photonic integrated circuits, and Universal Chiplet Interconnect Express (UCIe).

Dec 5, 2024
Advancing Software-Defined, Silicon-Optimized Data Centers

From silicon IP & semiconductor chip design software to digital twins, explore the technology advancing software-defined data centers for AI & HPC during SC24.

Nov 21, 2024
World's First CXL 3.1 Multi-Vendor Interoperability Demo Showcases New Memory Possibilities for Hyperscale Data Centers

Learn about the world's first CXL 3.1 standard multi-vendor interoperability demo, which we showcased with Teledyne LeCroy at the SC24 conference in Atlanta.

Nov 20, 2024
AI Startups are Using the Cloud to Accelerate Chip Design and Time-to-Market

We explore how AI chip startups Rain AI, Mentium, and TetraMem leverage cloud-based EDA tools to develop AI accelerator chips and co-processors better, faster.

Nov 18, 2024
Demonstrating the Future of 800G Ethernet at ECOC 2024

We joined the Ethernet Alliance to showcase the 800G ethernet standard at ECOC 2024, demonstrating a live network with switches, routers, and interconnects.

Nov 13, 2024
Post-Quantum Cryptography: Safeguarding the Future of Digital Security

Learn about post-quantum cryptography algorithms, NIST post-quantum cryptography standards, and the security promise of quantum-resistant algorithms.

Nov 11, 2024
Flash Forward: MRAM and RRAM Bring Embedded Memory and Applications into the Future

We explain what non-volatile memory is and why RRAM and MRAM (Resistive and Magneto-Resistive Random Access Memory) are taking over for embedded flash memory.

Oct 30, 2024
Hardware-Assisted Verification: Unlocking the Future of Chip and System Design

We explain what Hardware-Assisted Verification (HAV) is and explore its impact on hardware architecture, software-defined solutions, and the chip design flow.

Oct 28, 2024
From TSMC A16 and Multi-Physics Flows to Photonics and AI-Driven Design Migrations: Synopsys Receives Multiple TSMC Partner of the Year Awards

From RF design migration to interface IP and multi-die chip design tools, we received multiple TSMC Partner of the Year awards at the 2024 OIP Ecosystem Forum.

Oct 22, 2024
Accelerating AI Chip Development and Reducing Risk with Pre-silicon, Secure, Cloud-based Emulation

Learn how to accelerate AI chip design simulation with cloud-based chip emulation tools for secure, pre-silicon chip validation in a flexible cloud environment.

Oct 21, 2024

Read more from the Synopsys New Horizons for Chip Design blog…

 

Chalk Talks Featuring Synopsys

Vector Funnel Methodology for Power Analysis from Emulation to RTL to Signoff
The shift left methodology can help lower power throughout the electronic design cycle. In this episode of Chalk Talk, William Ruby from Synopsys and Amelia Dalton explore the biggest energy efficiency design challenges facing engineers today, how Synopsys can help solve a variety of energy efficiency design challenges and how the shift left methodology can enable consistent power efficiency and power reduction.
Jul 29, 2024
103,023 views
Accelerating Tapeouts with Synopsys Cloud and AI
In this episode of Chalk Talk, Amelia Dalton and Vikram Bhatia from Synopsys explore how you can accelerate your next tapeout with Synopsys Cloud and AI. They also discuss new enhancements and customer use cases that leverage AI with hybrid cloud deployment scenarios, and how this platform can help CAD managers and engineers reduce licensing overheads and seamlessly run complex EDA design flows through Synopsys Cloud.
Jul 8, 2024
42,753 views
SLM Silicon.da Introduction
In this episode of Chalk Talk, Amelia Dalton and Guy Cortez from Synopsys investigate how Synopsys’ Silicon.da platform can increase engineering productivity and silicon efficiency while providing the tool scalability needed for today’s semiconductor designs. They also walk through the steps involved in a SLM workflow and examine how this open and extensible platform can help you avoid pitfalls in each step of your next IC design.
Dec 6, 2023
62,713 views
One Year of Synopsys Cloud: Adoption, Enhancements and Evolution
The adoption of the cloud in the design automation industry has encouraged innovation across the entire semiconductor lifecycle. In this episode of Chalk Talk, Amelia Dalton chats with Vikram Bhatia from Synopsys about how Synopsys is redefining EDA in the Cloud with the industry’s first complete browser-based EDA-as-a-Service cloud platform. They explore the benefits that this on-demand pay-per use, web-based portal can bring to your next design. 
Jul 11, 2023
40,401 views
Automated Benchmark Tuning
Benchmarking is a great way to measure the performance of computing resources, but benchmark tuning can be a very complicated problem to solve. In this episode of Chalk Talk, Nozar Nozarian from Synopsys and Amelia Dalton investigate Synopsys’ Optimizer Studio that combines an evolution search algorithm with a powerful user interface that can help you quickly setup and run benchmarking experiments with much less effort and time than ever before.
Jan 26, 2023
41,223 views
Expanding SiliconMAX SLM to In-Field
In order to keep up with the rigorous pace of today’s electronic designs, we must have visibility into each step of our IC design lifecycle including debug, bring up and in-field operation. In this episode of Chalk Talk, Amelia Dalton chats with Steve Pateras from Synopsys about in-field infrastructure for silicon lifecycle management, the role that edge analytics play when it comes to in-field optimization, and how cloud analytics, runtime agents and SiliconMAX sensor analytics can provide you more information than ever before for the lifecycle of your IC design.
Jan 24, 2022
42,600 views
10X Faster Analog Simulation with PrimeSim Continuum
IC design has come a very long way in a short amount of time. Today, our SoC designs frequently include integrated analog, 100+ Gigabit data rates and 3D stacked DRAM integrated into our SoCs on interposers. In order to keep our heads above water in all of this IC complexity, we need a unified circuit simulation workflow and a fast signoff SPICE and FastSPICE architecture. In this episode of Chalk Talk, Amelia Dalton chats with Hany Elhak from Synopsys about how the unified workflow of the PrimeSim Continuum from Synopsys can help you address systematic and scale complexity for your next IC design.
Nov 1, 2021
43,379 views
Yield Explorer and SiliconDash
Once a design goes to tape-out, the real challenges begin. Teams find themselves drowning in data from design-process-test during production ramp-up, and have to cope with data from numerous sources in different formats in the manufacturing test supply chain. In this episode of Chalk Talk, Amelia Dalton chats with Mark Laird of Synopsys in part three of our series on the Silicon LifeCycle Management (SLM) platform, discussing how Yield Explorer and SiliconDash give valuable insight to engineering and manufacturing teams.
Apr 12, 2021
44,505 views

 

Synopsys Designer’s Digest

Elevate Your Chip Design and Development with Synopsys.ai
Award-winning Synopsys.ai, the industry’s first full stack, AI-driven electronic design automation suite, offers AI-driven workflow optimization & data analytics solutions along with breakthrough generative AI capabilities for next-level chip design.
Dec 8, 2023
Universal Verification Methodology Coverage for Bluespec RISC-V Cores
This whitepaper explains the basics of UVM functional coverage for RISC-V cores using the Google RISCV-DV open-source project, Synopsys verification solutions, and a RISC-V processor core from Bluespec.
Dec 7, 2023
An Automated Method for Adding Resiliency to Mission-Critical SoC Designs
Adding safety measures to SoC designs in the form of radiation-hardened elements or redundancy is essential in making mission-critical applications in the A&D, cloud, automotive, robotics, medical, and IoT industries more resilient against random hardware failures that occur. This paper discusses the automated process of implementing the safety mechanisms/measures (SM) in the design to make them more resilient and analyze their effectiveness from design inception to the final product.
Aug 23, 2023
Improving Design Robustness and Efficiency for Today’s Advanced Nodes
Learn how designers can take advantage of new ways to efficiently pinpoint voltage bottlenecks, drive voltage margin uniformity, and uncover opportunities to fine-tune operating voltages using PrimeShield design robustness solution.
Sep 28, 2021

 

Featured Videos from Synopsys

Tackling Challenges in 3DHI Microelectronics for Aerospace, Government, and Defense
Aerospace, Government, and Defense industry experts discuss the complexities of 3DHI for technological, manufacturing, & economic intricacies, as well as security, reliability, and safety challenges & solutions. Explore DARPA’s NGMM plan for the 3DHI R&D ecosystem.
Feb 14, 2024
24,622 views
Shape The Future Now with Synopsys ARC-V Processor IP
Synopsys ARC-V™ Processor IP delivers the optimal power-performance-efficiency and extensibility of ARC processors with broad software and tools support from Synopsys and the expanding RISC-V ecosystem. Built on the success of multiple generations of ARC processor IP covering a broad range of processor implementations, including functional safety (FS) versions, the ARC-V portfolio delivers what you need to optimize and differentiate your SoC.
Feb 1, 2024
26,109 views
Synopsys PCIe 6.0 End-to-End Hardware Linkup and Performance at PCI-SIG DevCon 2023
Join Gary Ruggles, Synopsys Product Manager for PCIe & CXL, at PCI-SIG DevCon 2023 and see Synopsys PCIe 6.0 Controller & PHY IP in an end-to-end host to device system, using Teledyne LeCroy's interposer & analyzer showing impact of payload size on throughput.
Jul 19, 2023
24,255 views
World's Most Interoperable PCIe 6.0 and Beyond at PCI-SIG DevCon 2023
See successful PCIe 6.0 interoperability demos in our booth & our partners’ booths at PCI-SIG DevCon 2023. Don’t miss our demo at 128 GT/s as we take a peek into the PCIe 7.0 tech and make sure to watch the world’s first PCIe 6.0 RX link training compliance tests.
Jul 19, 2023
25,713 views
Synopsys 224G Ethernet PHY IP Interop at TSMC Symposium 2023
At TSMC Symposium 2023 we showcased a successful 224G Ethernet PHY IP interop demonstration with backplane channels. Watch the various plots, ADC histogram and excellent eye diagrams results.
Jul 11, 2023
25,863 views
Synopsys 224G Ethernet PHY IP Wide-Open TX PAM-4 Eye
Watch this video of Synopsys 224G Ethernet PHY IP demonstrating wide-open TX PAM-4 eyes using Keysight’s oscilloscope & Samtec’s cables and connectors.
Jul 11, 2023
25,279 views
Synopsys End-to-End Solution for Glitch Power Analysis and Optimization
As glitch power becomes a growing component of total power, managing it requires a holistic solution for analysis and optimization from architecture to signoff. Watch this video and learn how to minimize glitch power in your designs.
Jun 15, 2023
25,878 views
Efficient Top-Level Interconnect Planning and Implementation with Synopsys IC Compiler II
This video shows how IC Compiler II and Fusion Compiler enable intelligent planning and implementation of complex interconnects through innovative Topological Interconnect Planning technology - accelerating schedules and achieving highest QoR.
Jun 6, 2023
25,457 views