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Self-driving cars. Machines that learn. Lightning-fast communication across billions of devices in the datasphere. Synopsys technology is at the heart of innovations that are changing the way people work and play in our era of Smart Everything. We provide the world’s most advanced technologies for chip design, verification, IP integration, and software security and quality testing. In short, we help our customers innovate from silicon to software so they can bring Smart Everything to life.

 

New Horizons for Chip Design

PCIe 6.x and 112 Gbps Ethernet: Synopsys and TeraSignal Achieve Optical Interconnect Breakthroughs

Discover Synopsys and TeraSignal's milestones in optical networking: PCIe 6.x and 112 Gbps Ethernet interoperability for hyperscale and HPC environments.

Jun 12, 2025
Software-Defined Vehicles: Agile Development with Cloud-Based Virtual Prototypes

Learn how cloud-based virtual prototypes accelerate software-defined vehicle (SDV) development, reduce costs, and improve time to market.

Jun 10, 2025
Synopsys Expands Collaboration with Arm to Accelerate the Automotive Industry’s Transformation to Software-Defined Vehicles

Discover how Synopsys and Arm are accelerating the shift to software-defined vehicles with innovative solutions for automotive system design and development.

Jun 4, 2025
High Bandwidth Memory (HBM) at the AI Crossroads: Customization or Standardization?

Discover how High Bandwidth Memory (HBM) is shaping AI's future. Explore the debate on customization vs. standardization and the impact on innovation.

May 28, 2025
Faster, More Collaborative SoC and Chiplet Architecture Exploration: Introducing Synopsys Platform Architect Development Kit (PADK)

Explore how Synopsys PADK revolutionizes SoC and chiplet design with cloud-based virtual prototyping, real-time collaboration, and secure data sharing.

May 22, 2025
Advancing Chip Design with AI: Synopsys AI Collaboration Featured at Microsoft Build

Discover how Synopsys and Microsoft are revolutionizing chip design with AI, redefining engineering workflows, and accelerating innovation.

May 19, 2025
Skymizer Reduces Verification Cycles for AI Accelerator IP Development by 33% with Synopsys HAPS Prototyping

Learn how Skymizer accelerated AI accelerator IP development by 33% with Synopsys HAPS prototyping, achieving faster validation and seamless integration.

May 19, 2025
Synopsys Interconnect IPs Enabling Scalable Compute Clusters

Learn how Synopsys Interconnect IPs enable scalable compute clusters, supporting next-gen AI with high bandwidth, interoperability, and efficient integration.

May 18, 2025
Multi-Die Design Challenges: Industry Leaders Provide Insights and Guidance

Explore common challenges and innovations in multi-die chip design, from AI tools to material advancements, driving performance for AI, HPC, and more.

May 15, 2025
AI in Engineering: How Technology is Reshaping Engineering Roles and Skills

AI in engineering is reshaping roles, automating tasks, and redefining skills. Explore what these changes mean and how to adapt in a shifting industry.

May 7, 2025
How AgentEngineer™ Technology Will Transform Engineering Workflows

Explore how AgentEngineer™ technology revolutionizes engineering workflows, enhancing productivity, innovation, and efficiency in the face of rising complexity.

May 6, 2025
Ethernet Evolution: Trends, Challenges, and the Future of Interoperability

Discover how evolving Ethernet standards drive AI, IoT, and data center innovation. Learn how Synopsys advances high-speed connectivity with 1.6T solutions.

Apr 30, 2025

Read more from the Synopsys New Horizons for Chip Design blog…

 

Chalk Talks Featuring Synopsys

Vector Funnel Methodology for Power Analysis from Emulation to RTL to Signoff
The shift left methodology can help lower power throughout the electronic design cycle. In this episode of Chalk Talk, William Ruby from Synopsys and Amelia Dalton explore the biggest energy efficiency design challenges facing engineers today, how Synopsys can help solve a variety of energy efficiency design challenges and how the shift left methodology can enable consistent power efficiency and power reduction.
Jul 29, 2024
246,990 views
Accelerating Tapeouts with Synopsys Cloud and AI
In this episode of Chalk Talk, Amelia Dalton and Vikram Bhatia from Synopsys explore how you can accelerate your next tapeout with Synopsys Cloud and AI. They also discuss new enhancements and customer use cases that leverage AI with hybrid cloud deployment scenarios, and how this platform can help CAD managers and engineers reduce licensing overheads and seamlessly run complex EDA design flows through Synopsys Cloud.
Jul 8, 2024
78,907 views
SLM Silicon.da Introduction
In this episode of Chalk Talk, Amelia Dalton and Guy Cortez from Synopsys investigate how Synopsys’ Silicon.da platform can increase engineering productivity and silicon efficiency while providing the tool scalability needed for today’s semiconductor designs. They also walk through the steps involved in a SLM workflow and examine how this open and extensible platform can help you avoid pitfalls in each step of your next IC design.
Dec 6, 2023
62,991 views
One Year of Synopsys Cloud: Adoption, Enhancements and Evolution
The adoption of the cloud in the design automation industry has encouraged innovation across the entire semiconductor lifecycle. In this episode of Chalk Talk, Amelia Dalton chats with Vikram Bhatia from Synopsys about how Synopsys is redefining EDA in the Cloud with the industry’s first complete browser-based EDA-as-a-Service cloud platform. They explore the benefits that this on-demand pay-per use, web-based portal can bring to your next design. 
Jul 11, 2023
40,447 views
Automated Benchmark Tuning
Benchmarking is a great way to measure the performance of computing resources, but benchmark tuning can be a very complicated problem to solve. In this episode of Chalk Talk, Nozar Nozarian from Synopsys and Amelia Dalton investigate Synopsys’ Optimizer Studio that combines an evolution search algorithm with a powerful user interface that can help you quickly setup and run benchmarking experiments with much less effort and time than ever before.
Jan 26, 2023
41,227 views
Expanding SiliconMAX SLM to In-Field
In order to keep up with the rigorous pace of today’s electronic designs, we must have visibility into each step of our IC design lifecycle including debug, bring up and in-field operation. In this episode of Chalk Talk, Amelia Dalton chats with Steve Pateras from Synopsys about in-field infrastructure for silicon lifecycle management, the role that edge analytics play when it comes to in-field optimization, and how cloud analytics, runtime agents and SiliconMAX sensor analytics can provide you more information than ever before for the lifecycle of your IC design.
Jan 24, 2022
42,600 views
10X Faster Analog Simulation with PrimeSim Continuum
IC design has come a very long way in a short amount of time. Today, our SoC designs frequently include integrated analog, 100+ Gigabit data rates and 3D stacked DRAM integrated into our SoCs on interposers. In order to keep our heads above water in all of this IC complexity, we need a unified circuit simulation workflow and a fast signoff SPICE and FastSPICE architecture. In this episode of Chalk Talk, Amelia Dalton chats with Hany Elhak from Synopsys about how the unified workflow of the PrimeSim Continuum from Synopsys can help you address systematic and scale complexity for your next IC design.
Nov 1, 2021
43,382 views
Yield Explorer and SiliconDash
Once a design goes to tape-out, the real challenges begin. Teams find themselves drowning in data from design-process-test during production ramp-up, and have to cope with data from numerous sources in different formats in the manufacturing test supply chain. In this episode of Chalk Talk, Amelia Dalton chats with Mark Laird of Synopsys in part three of our series on the Silicon LifeCycle Management (SLM) platform, discussing how Yield Explorer and SiliconDash give valuable insight to engineering and manufacturing teams.
Apr 12, 2021
44,507 views

 

Synopsys Designer’s Digest

Elevate Your Chip Design and Development with Synopsys.ai
Award-winning Synopsys.ai, the industry’s first full stack, AI-driven electronic design automation suite, offers AI-driven workflow optimization & data analytics solutions along with breakthrough generative AI capabilities for next-level chip design.
Dec 8, 2023
Universal Verification Methodology Coverage for Bluespec RISC-V Cores
This whitepaper explains the basics of UVM functional coverage for RISC-V cores using the Google RISCV-DV open-source project, Synopsys verification solutions, and a RISC-V processor core from Bluespec.
Dec 7, 2023
An Automated Method for Adding Resiliency to Mission-Critical SoC Designs
Adding safety measures to SoC designs in the form of radiation-hardened elements or redundancy is essential in making mission-critical applications in the A&D, cloud, automotive, robotics, medical, and IoT industries more resilient against random hardware failures that occur. This paper discusses the automated process of implementing the safety mechanisms/measures (SM) in the design to make them more resilient and analyze their effectiveness from design inception to the final product.
Aug 23, 2023
Improving Design Robustness and Efficiency for Today’s Advanced Nodes
Learn how designers can take advantage of new ways to efficiently pinpoint voltage bottlenecks, drive voltage margin uniformity, and uncover opportunities to fine-tune operating voltages using PrimeShield design robustness solution.
Sep 28, 2021

 

Featured Videos from Synopsys

Tackling Challenges in 3DHI Microelectronics for Aerospace, Government, and Defense
Aerospace, Government, and Defense industry experts discuss the complexities of 3DHI for technological, manufacturing, & economic intricacies, as well as security, reliability, and safety challenges & solutions. Explore DARPA’s NGMM plan for the 3DHI R&D ecosystem.
Feb 14, 2024
24,665 views
Shape The Future Now with Synopsys ARC-V Processor IP
Synopsys ARC-V™ Processor IP delivers the optimal power-performance-efficiency and extensibility of ARC processors with broad software and tools support from Synopsys and the expanding RISC-V ecosystem. Built on the success of multiple generations of ARC processor IP covering a broad range of processor implementations, including functional safety (FS) versions, the ARC-V portfolio delivers what you need to optimize and differentiate your SoC.
Feb 1, 2024
26,112 views
Synopsys PCIe 6.0 End-to-End Hardware Linkup and Performance at PCI-SIG DevCon 2023
Join Gary Ruggles, Synopsys Product Manager for PCIe & CXL, at PCI-SIG DevCon 2023 and see Synopsys PCIe 6.0 Controller & PHY IP in an end-to-end host to device system, using Teledyne LeCroy's interposer & analyzer showing impact of payload size on throughput.
Jul 19, 2023
24,255 views
World's Most Interoperable PCIe 6.0 and Beyond at PCI-SIG DevCon 2023
See successful PCIe 6.0 interoperability demos in our booth & our partners’ booths at PCI-SIG DevCon 2023. Don’t miss our demo at 128 GT/s as we take a peek into the PCIe 7.0 tech and make sure to watch the world’s first PCIe 6.0 RX link training compliance tests.
Jul 19, 2023
25,714 views
Synopsys 224G Ethernet PHY IP Interop at TSMC Symposium 2023
At TSMC Symposium 2023 we showcased a successful 224G Ethernet PHY IP interop demonstration with backplane channels. Watch the various plots, ADC histogram and excellent eye diagrams results.
Jul 11, 2023
25,863 views
Synopsys 224G Ethernet PHY IP Wide-Open TX PAM-4 Eye
Watch this video of Synopsys 224G Ethernet PHY IP demonstrating wide-open TX PAM-4 eyes using Keysight’s oscilloscope & Samtec’s cables and connectors.
Jul 11, 2023
25,282 views
Synopsys End-to-End Solution for Glitch Power Analysis and Optimization
As glitch power becomes a growing component of total power, managing it requires a holistic solution for analysis and optimization from architecture to signoff. Watch this video and learn how to minimize glitch power in your designs.
Jun 15, 2023
25,879 views
Efficient Top-Level Interconnect Planning and Implementation with Synopsys IC Compiler II
This video shows how IC Compiler II and Fusion Compiler enable intelligent planning and implementation of complex interconnects through innovative Topological Interconnect Planning technology - accelerating schedules and achieving highest QoR.
Jun 6, 2023
25,457 views