Learn how analog and mixed-signal (AMS) verification technology, which we developed as part of DARPA's POSH and ERI programs, emulates analog designs.

We explore how formal verification tools synergize with simulation technology to accelerate coverage closure in the SoC design and verification process.

We're joining Intel Foundry Services' USMAG (United States Military, Aerospace and Government) Alliance to help bolster US semiconductor design & manufacturing.

See how silicon remastering eases the chip supply shortage by migrating old designs to modern process nodes to expand semiconductor manufacturing capacity.

Learn how process design kits (PDKs) accelerate photonic integrated circuit design with IC building blocks including waveguides, phase shifters, and more.

We share 4 strategies for protecting advanced SoCs & chip designs, including chip design tools embedded with security standards & third-party certifications.

Explore the SOAFEE project's cloud-native virtual prototyping for connected vehicle applications and ADAS systems in the era of software-defined vehicles.

For National STEM Day 2022 we connected with up-and-coming R&D engineers on their STEM career pathways and key motivations, experiences, and role models.

Learn how our standard cell library characterization collaboration with TSMC helps chip designers achieve fast, accurate signoff for advanced process designs.

Learn how we're expanding diversity and empowering women in tech with a new career mentorship program through the global WomenTech network.

We're enabling secure SoC design for aerospace applications with cloud-based EDA tools on the Microsoft Azure Government Cloud, as part of the DoD's RAMP program.

Learn how formal equivalence checking and functional ECO tools accelerate SoC verification and streamline chip design signoff with machine learning.

In order to keep up with the rigorous pace of today’s electronic designs, we must have visibility into each step of our IC design lifecycle including debug, bring up and in-field operation. In this episode of Chalk Talk, Amelia Dalton chats with Steve Pateras from Synopsys about in-field infrastructure for silicon lifecycle management, the role that edge analytics play when it comes to in-field optimization, and how cloud analytics, runtime agents and SiliconMAX sensor analytics can provide you more information than ever before for the lifecycle of your IC design.

IC design has come a very long way in a short amount of time. Today, our SoC designs frequently include integrated analog, 100+ Gigabit data rates and 3D stacked DRAM integrated into our SoCs on interposers. In order to keep our heads above water in all of this IC complexity, we need a unified circuit simulation workflow and a fast signoff SPICE and FastSPICE architecture. In this episode of Chalk Talk, Amelia Dalton chats with Hany Elhak from Synopsys about how the unified workflow of the PrimeSim Continuum from Synopsys can help you address systematic and scale complexity for your next IC design.

Once a design goes to tape-out, the real challenges begin. Teams find themselves drowning in data from design-process-test during production ramp-up, and have to cope with data from numerous sources in different formats in the manufacturing test supply chain. In this episode of Chalk Talk, Amelia Dalton chats with Mark Laird of Synopsys in part three of our series on the Silicon LifeCycle Management (SLM) platform, discussing how Yield Explorer and SiliconDash give valuable insight to engineering and manufacturing teams.

In-chip monitoring can significantly alter the lifecycle management landscape. By taking advantage of modern techniques, today’s more complex designs can be optimized even after they are deployed. In this episode of Chalk Talk, Amelia Dalton chats with Stephen Crosher of Synopsys about silicon lifecycle management and how to take full advantage of the optimization opportunities available for scalability, reliability, and much more.

Wouldn’t it be great if we could keep on analyzing our IC designs once they are in the field? After all, simulation and lab measurements can never tell the whole story of how devices will behave in real-world use. In this episode of Chalk Talk, Amelia Dalton chats with Randy Fish of Synopsys about gaining better insight into IC designs through the use of embedded monitors and sensors, and how we can enable a range of new optimizations throughout the lifecycle of our designs.

Physical verification of IC designs at today’s advanced process nodes requires an immense amount of processing power. But, getting your design and verification tools to take full advantage of the compute resources available can be a challenge. In this episode of Chalk Talk, Amelia Dalton chats with Manoz Palaparthi of Synopsys about dramatically improving the performance of your physical verification process. 

Physical verification can take an enormous amount of time, and catching errors early in the process is the best way to avoid costly and time-consuming iterations. In this episode of Chalk Talk, Amelia Dalton chats with Christen Decoin of Synopsys about accelerating physical design productivity with tools and methods that can help catch errors earlier in the design process.

Learn how designers can take advantage of new ways to efficiently pinpoint voltage bottlenecks, drive voltage margin uniformity, and uncover opportunities to fine-tune operating voltages using PrimeShield design robustness solution.

What’s driving the need for a best-in-class solution for library characterization? In the latest Synopsys Designer’s Digest, learn about various SoC design challenges, requirements, and innovative technologies that deliver faster time-to-market with golden signoff quality. Learn how Synopsys’ PrimeLib™ solution addresses the increase in complexity and accuracy needs for advanced nodes and provides designers and foundries accelerated turn-around time and compute resource optimization.

Drive power optimization with actual workloads and continually refresh vectors at each step of chip implementation for maximum power savings.

Learn about Synopsys' collaboration with DARPA and other partners to develop a one-of-a-kind, high-performance AMS silicon verification capability. Please watch the video interview or read it online.

Watch the video to see how Perceive Ergo SoC with integrated Synopsys ARC Processor and Security IP delivers high-performance computing with ultra-low power for edge devices.

Watch the video to see how Inuitive’s NU4000 3D imaging and vision processor with an integrated Synopsys ARC EV processor delivers highly accurate and high-throughput depth sensing capabilities for drones, robotics, and other smart edge devices.

Learn how Synopsys’ ARC NPX NPU IP, featuring up to 96K MACs with enhanced utilization, new sparsity features and new interconnect for scalability, addresses the demands of real-time compute with ultra-low power consumption for AI applications.

We sat down with Jigesh Patel, Technical Marketing Manager of Photonic Solutions at Synopsys, to learn the challenges and benefits of using photonics in Aerospace and Defense systems.

This PCI-SIG DevCon 2022 video shows the industry’s first complete hardware demo of PCIe 6.0 with an end-to-end system from root complex to endpoint. The demo uses the Synopsys PCIe 6.0 Controller and PHY IP and shows successful link up and performance metrics.

Do you want faster runtime and better QoR? Watch this video to learn more about the latest innovation in the industry’s first, most trusted, and market-leading RTL synthesis solution: Synopsys Design Compiler® NXT