Explore our 2022 environmental, social, and governance (ESG) report to explore our sustainable business practices and our progress in building a smart future.

Accelerate vision transformer models and convolutional neural networks for AI vision systems with the ARC NPX6 NPU IP, the best processor for edge AI devices.

Multi-die systems are the future of the semiconductor industry; explore the role of 3D packaging and chiplet standards including UCIe in our trends report.

Explore the design challenges of integrated thermal management solutions for multi-die systems, and how AI-enabled EDA tools help, as covered at SNUG 2023.

Chip designers are rapidly migrating to EDA tools in the cloud; learn why and explore trends in chip design tools from our panel at SNUG Silicon Valley 2023.

Explore how semiconductor companies integrate chiplets and heterogeneous dies in multi-die systems to power everything from autonomous driving to generative AI.

Chip designers are rapidly migrating to EDA tools in the cloud; learn why and explore trends in chip design tools from our panel at SNUG Silicon Valley 2023.

At SNUG Silicon Valley 2023 we hosted a panel on AI in chip design, exploring how AI-enabled EDA tools simplify SoC design, accelerate verification, and more.

Learn how low power chip design verification can be shifted left in the SoC design flow, allowing chip designers to clean up UPF issues before RTL is ready.

See how our acquisition of Silicon Frontline Technology enhances IC design tools for power semiconductor devices through power device design & ESD verification.

Learn how Impare uses cloud-based chip design verification tools and explore the time, scalability and collaboration advantages of EDA tools in the cloud.

Explore the Compute Express Link (CXL) protocol and learn how it uses memory pooling to reduce latency for high-performing computing (HPC) systems via PCIe.

Benchmarking is a great way to measure the performance of computing resources, but benchmark tuning can be a very complicated problem to solve. In this episode of Chalk Talk, Nozar Nozarian from Synopsys and Amelia Dalton investigate Synopsys’ Optimizer Studio that combines an evolution search algorithm with a powerful user interface that can help you quickly setup and run benchmarking experiments with much less effort and time than ever before.

In order to keep up with the rigorous pace of today’s electronic designs, we must have visibility into each step of our IC design lifecycle including debug, bring up and in-field operation. In this episode of Chalk Talk, Amelia Dalton chats with Steve Pateras from Synopsys about in-field infrastructure for silicon lifecycle management, the role that edge analytics play when it comes to in-field optimization, and how cloud analytics, runtime agents and SiliconMAX sensor analytics can provide you more information than ever before for the lifecycle of your IC design.

IC design has come a very long way in a short amount of time. Today, our SoC designs frequently include integrated analog, 100+ Gigabit data rates and 3D stacked DRAM integrated into our SoCs on interposers. In order to keep our heads above water in all of this IC complexity, we need a unified circuit simulation workflow and a fast signoff SPICE and FastSPICE architecture. In this episode of Chalk Talk, Amelia Dalton chats with Hany Elhak from Synopsys about how the unified workflow of the PrimeSim Continuum from Synopsys can help you address systematic and scale complexity for your next IC design.

Once a design goes to tape-out, the real challenges begin. Teams find themselves drowning in data from design-process-test during production ramp-up, and have to cope with data from numerous sources in different formats in the manufacturing test supply chain. In this episode of Chalk Talk, Amelia Dalton chats with Mark Laird of Synopsys in part three of our series on the Silicon LifeCycle Management (SLM) platform, discussing how Yield Explorer and SiliconDash give valuable insight to engineering and manufacturing teams.

In-chip monitoring can significantly alter the lifecycle management landscape. By taking advantage of modern techniques, today’s more complex designs can be optimized even after they are deployed. In this episode of Chalk Talk, Amelia Dalton chats with Stephen Crosher of Synopsys about silicon lifecycle management and how to take full advantage of the optimization opportunities available for scalability, reliability, and much more.

Wouldn’t it be great if we could keep on analyzing our IC designs once they are in the field? After all, simulation and lab measurements can never tell the whole story of how devices will behave in real-world use. In this episode of Chalk Talk, Amelia Dalton chats with Randy Fish of Synopsys about gaining better insight into IC designs through the use of embedded monitors and sensors, and how we can enable a range of new optimizations throughout the lifecycle of our designs.

Physical verification of IC designs at today’s advanced process nodes requires an immense amount of processing power. But, getting your design and verification tools to take full advantage of the compute resources available can be a challenge. In this episode of Chalk Talk, Amelia Dalton chats with Manoz Palaparthi of Synopsys about dramatically improving the performance of your physical verification process. 

Physical verification can take an enormous amount of time, and catching errors early in the process is the best way to avoid costly and time-consuming iterations. In this episode of Chalk Talk, Amelia Dalton chats with Christen Decoin of Synopsys about accelerating physical design productivity with tools and methods that can help catch errors earlier in the design process.

Learn how designers can take advantage of new ways to efficiently pinpoint voltage bottlenecks, drive voltage margin uniformity, and uncover opportunities to fine-tune operating voltages using PrimeShield design robustness solution.

What’s driving the need for a best-in-class solution for library characterization? In the latest Synopsys Designer’s Digest, learn about various SoC design challenges, requirements, and innovative technologies that deliver faster time-to-market with golden signoff quality. Learn how Synopsys’ PrimeLib™ solution addresses the increase in complexity and accuracy needs for advanced nodes and provides designers and foundries accelerated turn-around time and compute resource optimization.

Synopsys’ industry-leading power analysis solution built on PrimePower technology that enables early RTL exploration, low power implementation and power signoff for design of energy-efficient SoCs.

Learn to translate a high-level power intent from CSV to a consumable UPF across a typical ASIC design flow using Verdi UPF Architect. Power Architect can focus on the efficiency of the Power Intent instead of worrying about Syntax & UPF Semantics.

This video demonstrates successful interoperability demonstrations of the Synopsys 224G and 112G Ethernet PHY IP, and the Synopsys PCIe 6.0 IP with third-party channels and SerDes.

In this video, Sr. R&D Engineer Rehan Iqbal, will guide you through Synopsys CXL IP passing compliance tests and demonstrating our seamless interoperability with Teladyne LeCroy Z516 Exerciser. This first-of-its-kind interoperability demo is a testament to Synopsys' commitment to delivering reliable IP solutions.

This Featured Video shows four demonstrations of the Synopsys 224G and 112G Ethernet PHY IP long and medium reach performance, interoperating with third-party channels and SerDes.

Find out how Synopsys ARC Software Test Library can help you stay within your power and area budget for high-performance safety-critical automotive design.

The demand for highly customized high-performance memory chips to cater to the needs of HPC, AI, and automotive applications is driving the need for new design paradigms such as DTCO, Design Shift Left, Digitization, and Design-for-Reliability.

Drive power optimization with actual workloads and continually refresh vectors at each step of chip implementation for maximum power savings.