Subscribe Now

Cadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality.

Cadence Blog – Latest Posts

Tensilica Vision Q8 and P1 DSPs, More AND Less
Apr 22, 2021
President George H. W. Bush famously said that he didn't do "the vision thing". Well, here at Cadence we definitely do the vision thing. In fact, the Tensilica Vision DSP product line...
Low-Power Implementation Training Videos
Apr 21, 2021
Hello Digital Designers, Interested in learning more about how to implement a low-power design? Do you have multiple voltage islands that need level-shifting, and isolation, and also require a CPF or...
Voltus Voice: Demystifying ESD — 5 Types of Checks to Bump up Your ESD Protection
Apr 21, 2021
Voltus TM IC Power Integrity Solution is a power integrity and analysis signoff solution that is integrated with the full suite of design implementation and signoff tools of Cadence to deliver the...
Start Your Engines: Seven Habits of Highly Efficient Mixed Signal Verification Engineers
Apr 21, 2021
Cadence ® Spectre ® AMS Designer is a high-performance mixed-signal simulation system. The ability to use multiple engines and drive from a variety of platforms enables you to "rev...
PSS2.0 is Out – Reflections on the Role of a Standard
Apr 21, 2021
We all know that a common language is the basis for every collaborative activity. This is true of natural languages and formal languages alike. In engineering, and specifically in the domain of...
(P)SpiceItUp: Search by Category, Description, or Function with PSpice Part Search
Apr 21, 2021
As a designer, your requirement at the early stages of schematic design is quite different, that is the part information you need when it comes to implementing the schematic design and while...
Embracing a Zero Trust Security Model
Apr 21, 2021
A couple of months ago, the National Security Agency (NSA) published a document titled Embracing a Zero Trust Security Model . I wrote about this topic almost exactly a year ago in my post From...
Brian Jackson Introduces a Mystery Product at IMAPS (Shh, It's OrbitIO)
Apr 20, 2021
I have been criticized in the past for calling OrbitIO the "red-headed stepchild" of the Cadence product line. I think I shall have to improve my positioning and simply call it "ahead...

Chalk Talks Featuring Cadence

Cloud Computing for Electronic Design (Are We There Yet?)
May 8, 2020
When your project is at crunch time, a shortage of server capacity can bring your schedule to a crawl. But, the rest of the year, having a bunch of extra servers sitting around idle can be extremely expensive. Cloud-based EDA lets you have exactly the compute resources you need, when you need them. In this episode of Chalk Talk, Amelia Dalton chats with Craig Johnson of Cadence Design Systems about Cadence’s cloud-based EDA solutions.
TensorFlow to RTL with High-Level Synthesis
Apr 17, 2020
Bridging the gap from the AI and data science world to the RTL and hardware design world can be challenging. High-level synthesis (HLS) can provide a mechanism to get from AI frameworks like TensorFlow into synthesizable RTL, enabling the development of high-performance inference architectures. In this episode of Chalk Talk, Amelia Dalton chats with Dave Apte of Cadence Design Systems about doing AI design with HLS.
Cadence Celsius Thermal Solver
Apr 13, 2020
Electrical-thermal co-simulation can dramatically improve the system design process, allowing thermal design adaptation to be done much earlier. The Cadence Celsius Thermal Solver is a complete electrical-thermal co-simulation solution for the full hierarchy of electronic systems from ICs to physical enclosures. In this episode of Chalk Talk, Amelia Dalton chats with CT Kao of Cadence Design Systems about how the Celsius Thermal Solver can help detect and mitigate thermal issues early in the design process.
Mom, I Have a Digital Twin? Now You Tell Me?
Apr 10, 2020
Today, one engineer’s “system” is another engineer’s “component.” The complexity of system-level design has skyrocketed with the new wave of intelligent systems. In this world, optimizing electronic system designs requires digital twins, shifting left, virtual platforms, and emulation to sort everything out. In this episode of Chalk Talk, Amelia Dalton chats with Frank Schirrmeister of Cadence Design Systems about system-level optimization.

Featured Content from Cadence

featured video
The Verification World We Know is About to be Revolutionized
Apr 12, 2021
Designs and software are growing in complexity. With verification, you need the right tool at the right time. Cadence® Palladium® Z2 emulation and Protium™ X2 prototyping dynamic duo address challenges of advanced applications from mobile to consumer and hyperscale computing. With a seamlessly integrated flow, unified debug, common interfaces, and testbench content across the systems, the dynamic duo offers rapid design migration and testing from emulation to prototyping. See them in action.
featured paper
Overcoming Signal Integrity Challenges of 112G Connections on PCB
Jan 4, 2021
One big challenge with 112G SerDes is handling signal integrity (SI) issues. By the time the signal winds its way from the transmitter on one chip to packages, across traces on PCBs, through connectors or cables, and arrives at the receiver, the signal is very distorted, making it a challenge to recover the clock and data-bits of the information being transferred. Learn how to handle SI issues and ensure that data is faithfully transmitted with a very low bit error rate (BER).
featured paper
Speeding Up Large-Scale EM Simulation of ICs Without Compromising Accuracy
Jan 4, 2021
With growing on-chip RF content, electromagnetic (EM) simulation of passives is critical — from selecting the right RF design candidates to detecting parasitic coupling. Being on-chip, accurate EM analysis requires a tie in to the process technology with process design kits (PDKs) and foundry-certified EM simulation technology. Anything short of that could compromise the RFIC’s functionality. Learn how to get the highest-in-class accuracy and 10X faster analysis.
featured video
Improve SoC-Level Verification Efficiency by Up to 10X
Nov 18, 2020
Chip-level testbench creation, multi-IP and CPU traffic generation, performance bottleneck identification, and data and cache-coherency verification all lack automation. The effort required to complete these tasks is error prone and time consuming. Discover how the Cadence® System VIP tool suite works seamlessly with its simulation, emulation, and prototyping engines to automate chip-level verification and improve efficiency by ten times over existing manual processes.