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The Future Faces of Tech: Meet Our 2022 GEM Fellowship Interns
Cadence is honored to partner with The National Graduate Engineering Minorities Consortium (GEM) as part of our mission to foster a diverse workforce in the STEM community. Throughout its four-decade history, GEM has connected bright and talented young minds from underrepresented groups to top companies, research facilities, and universities. This summer, we are thrilled to have five incredible students join our Cadence team as GEM Fellows. Throughout the course of their internship, they will have the opportunity to apply their field of study to the ways in which Cadence is shaping the world of technology, which includes innovations in 5G, computational fluid dynamics (CFD), and artificial intelligence (AI). GEM Fellows will also have the chance to grow their professional network by connecting with other interns and influential leaders at Cadence through our series of global intern events, as well as contribute to Inclusion Groups by providing important feedback that helps to further expand equity and inclusion in technology. GEM Fellows will be collaborating with innovators across the organization and will use their new skills to advance their future career goals. We are proud to showcase the impact of the fellows’ accomplishments at Cadence, as well as share their post-graduation pursuits. Each of them brings unique ideas and perspectives, strengthening our One Cadence—One Team culture. Get to know our GEM Fellows and hear what they had to say about their experience: Kayla Thames, Georgia Institute of Technology Studying to achieve a PhD in Electrical and Computer Engineering, Kayla is driven to own a tech start-up that helps small business owners thrive. She is also excited to return to academic life with more effective multitasking skills, something she has improved upon during her time at Cadence. What has been the most exciting part of your internship at Cadence? The most exciting part of my internship at Cadence is that I have the opportunity to test and critique the software that my group is currently developing. How has being a GEM Fellow impacted you? Being a GEM Fellow has opened the doors for so many new experiences and opportunities. I am truly appreciative of the GEM Fellowship and all their work to provide opportunities, such as this internship with Cadence, to myself and other minorities. Why did you decide to intern at Cadence? I decided to intern at Cadence because not only was I impressed with the work and efforts made by the company, but I also had a great experience with my recruiter and interviewer, which made the decision to join Cadence a no-brainer. Saidi Williams, John Hopkins University Returning to Cadence for a second year, Saidi plans to complete his Electrical Engineering Master’s program in 2023. Saidi has most enjoyed expanding his understanding of the impact Cadence tools have on chip design, development, manufacturing, and the industry worldwide. Welcome back, Saidi! How has being a GEM Fellow impacted you? Being a GEM Fellow has impacted me in ways I could only dream of. I’ve not only had the opportunity to go to graduate school for free but also the opportunity to work alongside and network with people from an amazing company and other people within GEM who have helped me develop technically and professionally. These opportunities have helped propel me to heights that I thought wouldn’t be possible until later in my life, and I’m very grateful! What do you hope to bring back to academic life from Cadence? I hope to bring back my newfound professional knowledge, technical knowledge, and further polished soft skills from this internship and apply them to the research for my Master’s thesis I’ll be starting this coming fall. What are your plans post-graduation? I want to find a worthwhile computer engineering job that correlates to GPU, SoC, motherboard, or general ASIC design. I also want to learn some more technical and financial skills so I can work toward becoming an entrepreneur. Rosemary Nwosu-Ihueze, University of Kentucky Currently pursuing an undergraduate degree in computer science with an expected graduation date in the Fall of 2023, Rosemary hopes to build an exciting user experience career in the human-computer interaction industry. What do you hope to bring back to academic life from Cadence? How not to complicate problem-solving! How has being a GEM Fellow impacted you? Meeting new people and the resolve to continue to graduate studies. Why did you decide to intern at Cadence? I decided to intern at Cadence after my interview with my current mentor (supervisor). The first impression was awesome! Carlos Ayala Bellido, Stanford University Beginning a new chapter at Stanford University this fall, Carlos will be propelling himself toward a Master’s of Science in computational and mathematical engineering, planning to graduate in 2024. He is excited to take with him a deeper understanding of corporate culture and a new facet of experience that can be applied, wholeheartedly, during his upcoming academic tenure and beyond. What has been the most exciting part of your internship at Cadence? The most exciting part of my internship at Cadence is challenging myself by learning a new language and a new type of programming style. The work I’ve done with SystemVerilog and scripting is not something I have really ever done in the past, and it’s taken work to get adjusted to it. For that same reason, it’s been exciting because it means I’m trying out new things and working towards new skills, especially knowing that this all culminates in work towards a project which could improve the quality of certain Cadence products. What are your plans post-graduation? After graduation, I plan to take a break from education for a bit and work on my software engineering career, potentially going into product management once I feel like I have sufficient experience. I would like to consider pursuing another Master’s degree or even a PhD, but I want to at least get the chance to explore my options and how I feel about industry work before considering academia. How has being a GEM Fellow impacted you? Being a GEM Fellow has greatly impacted me because, prior to that, I had not considered graduate studies as an option. Even as I applied to some graduate programs in the fall, I did so more out of a promise to myself to see what my options could be rather than what I realistically had access to. Graduate studies were financially out of my reach, so to hear that I would be a GEM Fellow suddenly made me realize I could consider these schools and pushed me towards my decision to place my full-time career on hold. Euler Valdiviseo, The Ohio State University Targeting a 2027 graduation, Euler will enter his PhD program in electrical engineering at The Ohio State University this Fall. Post-graduation, Euler is motivated to join a company like Cadence where he can develop technologies that improve quality of life and help those who need it the most. How has being a GEM Fellow impacted you? The GEM Scholarship Program has allowed me to gain valuable work experience and skills through my internship at Cadence. It has also provided me with an academic year fellowship, which will allow me to afford my education. Receiving the GEM scholarship told me that I am seen as someone who has the ability to contribute to the future of our society. It brought me one step closer to achieving my goals. Why did you decide to intern at Cadence? I decided to intern at Cadence because it is a pivotal leader in electronic system design, which is an interest of mine. I was very excited to work in a company whose customers are the world’s most innovative companies, delivering fascinating electronic products to different markets, such as automotive and aerospace. What has been the most exciting part of your internship at Cadence? The most exciting part of my internship at Cadence has been learning new things, such as implementing a design with the RTL-to-GDSII flow and functional safety. In addition, it has been fascinating to be able to work with people who have the same goal as I do, which is to be able to help develop technologies that will help society.
Metaverse for Semiconductor Design: What to Expect?
What is the metaverse, and how does it help to accelerate the speed of innovation in semiconductors? The metaverse is a man-made virtual world. It is an immersive, online space created by the convergence of digital and physical reality. It is a combination of virtual reality (VR ), augmented reality (AR) , mixed reality (MR) , blockchain, web3 , cryptocurrencies, social media, and more. Big companies are competing to create a metaverse platform, aka an operating system for the metaverse. The metaverse uses semiconductors and is used to make semiconductor designs. HPC , cloud , edge computing , artificial intelligence (AI) , and many more are helping to design metaverse, and the metaverse can help to accelerate the innovation time and reduce the cost of semiconductor design. What is Metaverse? Things are changing fast, and one of the most outstanding achievements is the rapid advancement of communication. We never had so many ways to communicate as we have now, from Graham Bell's telephone to the latest gig, the metaverse. The metaverse is the point of convergence digital and physical world, as shown below, where people will create, work, play, socialize and transact in a fully functioning economy that rivals the physical world. Imagine you wear your glasses/headsets and are virtually in your home space. The man-made metaverse brings people, places, and things together with the digital world in the consumer and enterprise world. How fascinating it is to transform avatars effortlessly! The metaverse uses augmented reality (AR), virtual reality (VR), artificial intelligence, language processing , blockchain , etc., to create this virtual world and needs The smooth metaverse operation needs the least latency, virtual compute, and storage services, and of course broadband connectivity. High-performance computing (HPC) is instrumental to the metaverse, as we need HPC for real-time data processing. Companies like Meta and NVIDIA collaborating to build AI supercomputers to power the metaverse. This technology is traditionally used in gaming, but recent developments showed that the metaverse is also incorporated in remote working. Many organizations are open to adopting it for education, games, and space exploration. NASA is planning to ride the metaverse wave: NASA's Martian metaverse will prepare astronauts for Mars Mission using Epic Games' engine for a practical and realistic environment. Metaverse and Semiconductors – How Do Semiconductors Help in the Making of Metaverse? The metaverse is best understood as a quasi-successor state to the mobile internet. This is because the metaverse will not fundamentally replace the internet but iteratively transform it. The semiconductor industry is creating chips to transform the future of our living; also, we are leveraging these technologies today to deploy these innovations smarter and faster. Semiconductors play a significant role in such innovations, from chip technology's ongoing evolution and creation of the unreal. Semiconductors are crucial in making the metaverse a reality. Existing chips are not best suited for connecting 3D worlds; supply chain and longer lead times are other challenges that limit the usage of existing chips for the metaverse. Key players have started designing chips to make metaverse a reality. For instance, Omniverse from NVIDIA for connecting 3D worlds into a shared universe. What is Semiverse? – The Semiconductor Metaverse A semiconductor metaverse can help to accelerate chip innovation and shorten the time from technology ideation to commercialization. There are many tools and complicated transitions involved during a complete design cycle. The semiverse is a virtual environment in which development and testing are done as a combined human-machine enterprise. Both humans and machines are doing what they do best. It will also enable greater collaboration to help the industry deliver disruptive technologies faster and more often. The complete digital representation of the entire chip fabrication process in the semiverse will allow chipmakers to look at the interactions across processes throughout the fab to improve repeatability and optimize yield. The term was coined at the Imec Future Summits conference by Lam Research's CEO, Tim Archer. "We envision the semiverse as a hybrid physical, virtual environment where development and testing is done as a joint human-machine enterprise, where humans and machines are actually each doing what they do best," Tim Archer, CEO of Lam Research Benefits of the Semiverse While the growth of the semiverse is expected to benefit semiconductor companies, it will also help startups and research labs as well, as it helps in: Connecting digital twins of the chips, equipment, and labs in a shared virtual space Tremendously reducing the new idea implementation and testing costs Helps startups and researchers could contribute more disruptive ideas to the ecosystem Although the industry is still far from fully realizing the semiverse, using the cloud for EDA is a big step. Emerging model-based engineering tools are already helping to virtualize more of the engineering and testing process. Challenges Associated with Metaverse The metaverse involves usage of AI/ML. It is very challenging to use these at the edge demands usage of tiny-ML and high-performance computing. Other challenges associated with metaverse are as below: It is a new technology, so significantly less data is available for AI/ML Improved data privacy and security along with data collection Verifying that system-on-chip (SoC) designs function correctly prior to manufacturing Least latency Low power /better energy efficiency Faster edge computing Virtualization of compute Cadence and the Metaverse Bringing industry-leading vSLAM to the edge using Tensilica Vision DSPs for glasses and HMDs, Cadence is working with semiconductor leaders to help them to innovate and build new ways to engage with customers, partners, and their digital workforce. Cadence provides Tensilica IPs and solutions like Always-On systems for low-energy internet of things (IoT) applications. Our verification suite helps to solve the compute needs of SoC verification on Arm-based server datacenters. Tensilica AI platform is a comprehensive IP platform for edge to on-device to accelerate AI everywhere. Such innovative solutions from Cadence help to extend the battery life and improve the user experience. www.youtube.com/watch Xvisio and Cadence collaborate to build a metaverse. It uses Cadence’sTensilica Vision Q7 and Q8 DSPs and Xtensa SDKs to create a metaverse. Learn more Xvisio and Cadence Work Together to Build the World a Metaverse Benedict Evans on Tech 2022 The reality in Your Glasses www.youtube.com/.../r44P5DM3Ifk
This Month in IDA
This month in IDA, we shared the news that X-FAB Silicon Foundries SE, an analog/mixed-signal and specialty foundry, has integrated the Cadence EMX Planar 3D Solver into its X-FAB RFIC workflow for current and future RF platforms designing innovative communication and automotive products. EMX solver validation of X-FAB RF reference designs for low-noise amplifiers, RF switches, filters, and passive elements all delivered high-accuracy results within very short timeframes. You can learn more here . A new blog from Sherry Hess shines a light on the concept of shifting left in multi-physics analysis to find and prevent defects early in the design process to improve electronic product and system quality and performance. IDA in the News X-FAB's Innovative Communication and Automotive Designs: Powered by Cadence EMX Planar 3D Solver Microwave Journal: IMS2022 Wrap Up IMS2022 Women in Microwaves Retrospective: We’ve Come a Long, Long Way New Collateral/Blogs SI/PI Simulation and Measurement Correlation Forum Shift Left: Moving Multiphysics into the Mainstream In-Design Analysis in the Cloud with Cadence OnCloud Cadence at IMS2022
The Father of Breakfast Bytes
Ian McLellan, 1928-2022 I will be away all next week in England. As you might guess from the subtitle above, I'm attending my father's funeral. He passed away recently at the age of 93. Normally, when I'm away, Breakfast Bytes goes dark, but this time, some of my colleagues will be guest-blogging, so Breakfast Bytes will appear every day (except Friday, which is a Cadence global recharge day). On the last day before a break, I almost always write an off-topic post, so today, I thought I'd write a brief biography of my father. It's not as off-topic as it sounds since he was an electrical engineer. Yes, the apple did not fall very far from the tree in my case. My Dad My Dad was born in 1928. Since he spent most of his career in the Royal Navy, this turned out to be very good timing for keeping out of harm's way. But I'm getting ahead of myself. My Dad's mother died when he was 14, which was 1942, so right in the middle of the war. His elder sister was a nurse, and so he ended up taking over doing all the cooking for a couple of years. I forget when I found that out, but it seemed very odd since he never cooked while I was growing up. Not even the sort of cooking I do where I cook and barbecue at weekends, but almost never cook during the week (at least pre-WFH). When my mother was dying in 1999, he immediately went back into his teenage mode and took over all the cooking, and after my mother's death, he cooked for himself until the last few months when he became too frail to look after himself. At 16, he joined the Royal Navy. He went to Dartmouth, the Navy's training school in Plymouth (yes, the same Plymouth that the Mayflower sailed from). That took a year, and so he completed his training when he was 17 in 1945, just as the war ended, so he never saw active service. Getting ahead of myself again, he retired from the Navy in about 1979 when he was just over 50. The Falklands War was in 1982, so he managed to miss that one too. In between, the Navy wasn't really involved in any wars that I can think of. Cambridge After the war, the Navy decided that it should train its engineers to a higher standard than it had previously by sending officers to University for the first time ever. So my Dad ended up at Cambridge University and studied engineering. Later, I would actually work for the Engineering department for six months and then go to Cambridge myself. Apples and trees again. During his three years at Cambridge, his future wife (aka my mother) was studying to be a PE Teacher at Bedford College of Physical Education, about 30 miles away. Undergraduates were not allowed cars, which I think was still the rule in my day, but somehow my Dad had one anyway, an Austin Cowley he apparently called Wilhemina because of its number plate. Also, my mother was very fit studying PE, so she would sometimes cycle the 30 miles. There are basically no hills between Bedford and Cambridge, so this wasn't as strenuous as it sounds. My parents got married in 1951, and my Dad's job was in Wales. After a short time there, my Dad went to sea for the first time, I think on HMS Resource. I was born while he was away, and at about the age of 1 my mother flew out to Malta with me, and my Dad got to see me for the first time. Polaris and Dr. No People joke that IBM stands for "I've been moved," but being what in the US is called a Navy Brat is definitely like that. We moved to Gillingham near Chatham dockyard, where my younger brother was born, then to just outside Bath. The Navy's R&D labs are in Bath. At first, that seems a bit odd since Bath is a long way from the coast, but Navies like to site the facilities that don't require ships and dockyards inland...so other Navies cannot get to them. Of course, Air Forces can, but the world over each service seems to act as if other services don't exist. You might think that the planes flown off aircraft carriers in the Royal Navy were run by the Royal Air Force, but no, by the Fleet Air Arm, part of the Navy (the US Navy is the same—for example, the display team the Blue Angels are part of the US Navy, not the USAF). We moved closer to the outskirts of Bath, and my parents bought their first house. There were many other moves, including moving to Gosport, near Portsmouth dockyard. In 1962, the US and UK signed an agreement to transfer the technology for the submarine-launched Polaris missiles to Britain. My Dad had received a 24-hour notice to report to his new job back outside Bath. He was one of the people in charge of transferring the missile technology and getting it built. Although the US supplied the missiles and the launch systems, the submarines and the warheads were provided by the UK. Also, in 1962, the first James Bond movie, Dr. No, came out. Decades later, my Dad told me that he was nicknamed Dr. No in this era since he insisted that no changes would be made to the US designs at all; they would build them exactly as on the drawings. Otherwise, he knew that the whole program would go off the rails. I'm sure it was one of the things that contributed to the program being completed ahead of schedule and under budget. My Dad's next tour of duty on a ship was on the aircraft carrier HMS Eagle. He was away for two years while I was in my mid-teens. When eventually the ship returned to the UK it was to Plymouth to be decommissioned. The family got to go out to the ship on a launch, and since my Dad was "commander L," he had to be on the bridge (L is for eLectrical since E is for Engineering), and we got to be there too. It was definitely an experience coming into the dockyard on the bridge! Retirement The Navy had a policy of "up or out." By then, my Dad was a Captain, although back to what he called "sailing a desk," that desk being...surprise...just outside Bath. But he never got promoted to an Admiral, so he was laid off (with a lump-sum payment and an inflation-adjusted pension). He and my mother moved to Cornwall and purchased a cottage with a lot of land and a stream running through it. My Dad constructed and ran a trout farm there for a decade before they sold that property, and he finally retired completely. My mother died in 1999, and so my father lived on his own for 23 years until just a few months ago, still in Cornwall. The picture below was his eightieth birthday (with my brother, and my two kids, his only grandchildren...my kids have no cousins). So next week I will be in Cornwall too, perhaps for the last time in my life. Sign up for Sunday Brunch, the weekly Breakfast Bytes email. .
Every year at the Design Automation Conference (DAC), John Cooley organizes what he calls the DAC Troublemakers' Panel . It used to be called the CEO Panel since the participants were CEOs. Early on, Joe Costello (Cadence's then-CEO) and Gerry Hsu (Avanti! CEO and previously a long-time Cadence executive) got into a literal shouting match. Magma's CEO and Synopsys' CEO refused to be on any panel together. It is always interesting! This year I expected to see Joe Sawicki, formerly of Mentor, now part of Siemens. But unfortunately, he had a bike accident, got a concussion, and was forbidden to fly, so the Siemens/Mentor slot was taken by Ravi Subramanian, who used to be the CEO of Berkeley Design Automation (BDA) until Mentor acquired it in 2014. The panel consisted of (from left to right in the above picture): Tony Carusone of AlphaWave Ravi Subramanian of Siemens EDA (fka Mentor Graphics) Dean Drako of IC Manage Tom Beckley of Cadence Prakash Narain of Real Intent Sam Appleton of Ausdia John Cooley, the moderator (or stirrer of the pot) All questions start with "Q" and were asked by John Cooley. Anything in [brackets] is my commentary. Q: Ravi, why are you here instead of Joe Sawicki? Ravi: He had a bike accident, broke a collar bone, had a bad concussion, and his doctor forbade him to fly. Q: Joe always gets the first question. So you do. Mentor acquired OneSpin just over a year ago. How will you compete with Jasper? Was the acquisition a mistake? Ravi: Jasper pioneered an app-based focus that expanded the market and enabled a much bigger user base. What we see is that Mentor, through the acquisition of Zero-In, had a solver first approach, but as the market went to app-based approach, we needed specialized apps. OneSpin was growing at 35% per year and growing into various vertical markets. Before the acquisition, Cadence had 55%, Synopsys 20%, OneSpin 25%, and Mentor 13%. The formal market is growing, and we expect to grow our #2 position and take on Jasper. Q: Dean, you were first on my panel in 2008. Doesn’t everyone already have a design data management (DDM) tool? Why are you here? Dean: As you know, the EDA market and semiconductors are both growing. DDM [Design Data Management] has expanded significantly. Back in 2008, we were mostly analog. We have since expanded into the digital realm. IP reuse has become huge. In order to keep winning and beating out the competition, we’ve had to drive our tool forward. We were always the fastest tool for DDM out there, but now we are 100X faster. With the geopolitical situation, DDM has got complex. A lot of companies have constraints on who can access what data. It’s a big issue. We’ve had to expand the number of design flows, and covering all of them in a large organization is important. Q: Since you mentioned the cloud, isn’t that your Achilles heel? Why go to you? Dean: ICmanage Holodeck is complementary to the major EDA vendors. It improves both naked cloud but also cloudburst. In order to get a workflow into the cloud, a whole load of things needs to happen…and the cloud can get expensive. Here’s some info on Xilinx. In order to speed up tool launch, you need to get all the data to the cloud in order to run it. IC Holodeck only moves exactly the data required. If you are moving 200TB to cloud, it costs a lot. We improve execution performance by optimizing the I/O. We just moved 2TB of the 200TB, so 99% saving. Reduced the runtime from 60 hours to 35 hours, just using caching technology included in Holodeck. In cloud you can pay for a lot of compute, but you don’t always get it due to I/O. It’s all about design data management and getting it in the right place. Q: Tom, you guys have cloud. Why isn’t Dean out of business? Tom: We love that people are using the cloud. And this morning we announced the acquisition of Future Facilities. We’re not here to put Dean out of business. But what we are interested in is how do we democratize design so everyone has access to tools. Q: Ravi, do you guys have cloud stuff? Ravi: All the three big EDA companies have cloud solutions since customers are asking for it. You can run in our cloud, point tool, batch mode, even our competitors' tools. Q: Prakash, you’ve been touting some mystery product at this DAC. So what’s going on with Real Intent? Prakash: It's a product we’ll be releasing shortly, a new product. I'm not going to name it; that’s why it’s a mystery product. This allows customers to create very custom static signoff solutions that cannot be generalized across different design houses. Users provide signoff requirements. It’s still a static timing signoff tool. Effectively users can create custom static signing solutions with this tool. This product was developed in partnership with a large customer, and they used to just have scripts. That would run slowly with no debug environment. So the new product is a combination of all these capabilities with minimal CAD effort. Dean: Why the secrecy about the name? Prakash: We are releasing it in a month. Dean: Who is the big company? Prakash: I can’t say, obviously. [In case you don't know, many big users of EDA tools forbid any sort of endorsement, either by their own people saying which tools they use or by EDA companies claiming a company as a customer] Q: Using a mystery product, can I use Spyglass CDC? Is this locking people into your product? Prakash: This handles requirements that are not met by other tools. Q: Tony, welcome to the panel. You are AlphaWave's CTO. In four years, AlphaWave went from founding to a miracle IPO. Why are you even working? Tony: I wasn’t here during that. I just joined recently. I want to see more growth going forward. Connectivity in the datacenter is where we are focused, and 80% of datacenter traffic is within the datacenter. So I’m happy to hear that since we sell datacenter connectivity IP. We focused on DSP-based transceiver architecture from the beginning. A thin analog part and the rest is digital DSP. We will have variants for 50 interfaces by the end of the year, PCI, Ethernet, long reach, short reach, and so on. Plus in all the technology variants 12nm, 7nm, 5nm, and 3nm. It's the right market and the right technology. The truth is it has not been only four years. I worked with the founding team 20 years ago, and this is three companies later. Q: There are some key technology limits there. How fast can you process data? Tony: Back when AlphaWave was getting started in 2017, it wasn’t clear if we could use parallel DSP processing and have PPA that renders the AMS transceivers obsolete. Upper frequency is 200 Gbps transceiver this year [presumably 224Gbps since that is the standard]. Q: How do you compete? Just by cutting prices? Tony: No, it’s all about PPA, not just price. We were TSMC's supplier of the year. Tom: Customers want bleeding edge, and many of them use TSMC. I’d like to get Tony as a more active customer of my tools. Q: Prakash, Mentor CDC and Spyglass have been pushing more on static signoff. How do you compete in that environment? Prakash: Customers continue to put more complex and larger designs and need to keep the same schedule, so we need further development of technology. It is very hard to scale and it requires continuous innovation. Announced new CDC. We are innovative on three dimensions. 30% improvement in capacity, multi-level organization of information for debug, and methodology and innovative use models. We are focused on creating faster and more robust static signoff. Q: Sam [finally], speaking of being a drain on the EDA customers’ budget. Everyone has PrimeTime, Tempus, etc., already. Why would they look at your tool? Sam: STA tools will run the constraints, but if the constraints have errors, you’ll have problems and may need respins. We are checking for clocking errors. Two examples. Chip #1 is a huge SoC with 3000 clocks and a good naming convention. The designer has to declare all these clock groups to stop getting an avalanche of false timing errors. It turns out that for one of these 3000 clocks they had used slightly wrong rules, causing an entire group of the chip not to be checked. The silicon didn’t work. They brought in Ausdia’s TimeVision and within hours had detected the problem. Q: Tom, in 2019, Anirudh [Devgan, now CEO of Cadence] declared war on HFSS by launching Clarity. So what’s happened? Tom: Clarity launched at the end of 2019. Data we were showing much higher capacity with the same accuracy as HFSS. No need to partition the design. From IP, to chip, to package, to board, all the lines are blurred. That’s what Clarity allows you to do. Q: Who are your customers? Tom: We’ve announced some, Mediatek, Renasas, some system companies we can’t name...but we are not talking just a few dozen customers. It's many, many more. Q: Ravi, how come you guys don’t have a 3DIC flow? Ravi: We do have a full 3DIC solution. Four parts: be able to do prototyping and planning, actual verification and testing, analysis engines to provide the insights, and finally, make sure designs are manufacturable. Both Cadence and Siemens/Mentor have been in this area for a decade. We’ve combined stuff from our packaging technology along with Calibre, so these are two critical parts. Also brought test in, since the test is fundamental as to whether having a testable solution, to dramatically reduce the test time. Also, Expedition SI, which is a front-end planning solution. It works with both Siemens EDA and Cadence solutions. Tony: We are designing chiplets, and this is to go beyond the reticle limit or to blend different technologies. Q: Ravi, roughly six months ago, you launched inPower Bluewave to a giant 3-way fight with Ansys, Cadence Voltus, and Voltus-Fi. Wally used to say you don’t want to be 3rd place. Ravi: Of course, nobody enters a market to be third, but the analysis needs are breaking the incumbent tools, so there is an opportunity to provide a disruptive change. Especially when there is a lot of digitally controlled analog, tools are breaking. There’s only one tool in the world that can handle this. We are only six months into the market, and we have customers that you’ve written about on DeepChip. On the digital side, Esperanto has a chip with 1000 RISC-V cores. 3.5B instances. You can’t do EMIR with any other tool. The problem has been dramatically changed. Q: Tom, do you have EMIR tool? Tom: Yes, we have Voltus and Voltus-FI. Q: How is it doing? Tom: We are growing at over 20%. Dean: I was just going to say 20% of 0 is still zero! Q: Who do you have for Voltus and Voltus-Fi Tom: 30% of Virtuoso customers. Q: Tom, Aart [CEO of Synopsys] has been doing really well in air war for AI. Synopsys AI is even in the New York Times, Forbes, etc. Making it look like they are kicking ass. Don’t you have marketing? Tom: I’m sure Synopsys is paying a lot of money to get published in the New York Times, and we’d rather invest in R&D. Q: Doesn’t that impact stock? You’ve got to woo wall street. Tom: AI is just getting started, and in many ways, now it is being used to dramatically change efficiency. The design space is too large, and we can help optimize without getting trapped in local minima. We can also do what-if analysis. Both on the chip side and chip-package-board. Q: Dean, what about AI? Dean: The key to AI is datasets. You have to have data. We do datasets at IC manage. AI is super application-focused. Dog or no-dog. Or 100 different animals. Think about that applied to EDA, we face thousands of different problems, and there will be an AI thing for each problem. Tom: You need to be careful since data is the customers' data. Dean: You are telling me customers need to do their own training? Tom: I’m saying customers own the large datasets. If you want to go across segments, that is their own data. Q: Ravi, two years ago, Joe [Sawicki, Siemens EDA] offered free licenses for AFS? Ravi: It depends on how is the price of one product influenced by the price of another product. One is cell characterization, very short run times. Also, long simulations for analog, and post-layout simulation take a dominant share of the simulation cycles. We had 200 AFS customers when we started this, and now they get 5-10X simulation speed, but the demand for licenses is dramatically larger. Layout is the design, so these are simulations sometimes taking days or weeks. 10X makes a week into a day, or a day into lunchtime, and so on. Tom: So many corners are being looked at right now. You can’t supply enough simulators. Q: Are you scaling your prices? Tom: We are seeing exponential growth across the board. Q: Tom, you had Palladium and Protium, and you leapfrog each other all the time. The one thing you had is unified compile. Are you about to lose to Ravi? Tom: We walk in the shoes of our customers since we are developing complex hardware with our own products. Q: Ravi, was buying Atoptech [actually called Avatar by then] a mistake. You will be #3 at best, and a distant #3. Ravi: You can’t get to #2 without being #3 first. It is brilliant technology. Place and route are one of the markets in EDA where inside you can be inside someone else’s moat. TSMC started certification at 7nm and 5nm, and Samsung too. 14 customers in 12 months that are not legacy users of Atoptech/Avatar. Q: Innovus is really known. Fusion Compiler is well known. Ravi: Absolutely. Innovus is there, and customers want a 3rd solution too. They need a robust enough environment for each tool. It is a node-by-node introduction. Each node warrants a completely new solution. What the world has presented is a new opportunity with the physics changing so much. Q: Charles Shi [Needham] said that in the next 12 months, there will be a recession. What will be the impact on EDA? Dean: Just look back; semiconductor is either boom or bust. We are in a boom now, but we are slow on the uptake, and then we build too much capacity and be in a bust. Prakash: I’m not too concerned. There will be some impact, but what our customers are engaged in doesn’t change. Sam: The product guys don't want to get behind when coming out of the cycle. Nobody wants to come out of the cycle and realize they are two years behind; Tom: They have to invest. Q [John]: Thank you. Sign up for Sunday Brunch, the weekly Breakfast Bytes email. .
Who to Read on Semiconductors
It's great that you're here. That means you read Breakfast Bytes, at least sometimes. But I am a generalist. There are lots of areas of the semiconductor ecosystem that I only cover superficially or don't cover at all. So who else should you read? Well, let me tell you who I read regularly. Fabricated Knowledge This is a Substack written by Doug. His name shows as Doug (mule) but @mule is the name he uses on Twitter so I don't think it is actually his last name. I ran into him at Semicon West, and he gave me a free subscription (normally $25/month), so I'm not sure quite how much you get on the free subscription level. His background is in finance, and much of what he writes is for that audience, analyzing financial results of the usual suspects in our industry. But he digs deeper into technology too, to get at the financial implications. For example, here is his post CXL: Protocol for Heterogenous Datacenters . SemiAnalysis SemiAnalysis is in transition from its own website to a substack. It is written by Dylan Patel. It is also focused on the analysis of the finance industry, but also digs into technical issues and their implications, and sometimes politics too. A post well worth reading is The Dark Side Of The Semiconductor Design Renaissance – Fixed Costs Soaring Due To Photomask Sets, Verification, and Validation to get a flavor of how he covers the industry. Scotten Jones When I worked at SemiWiki , one of my co-bloggers was Scotten Jones. I usually meet him at least once a year since both of us attend IEDM in San Francisco each December. I've also met him at ITF (imec Technology Forum) in Belgium. His day job is running IC Knowledge . Scotten is the go-to person for anything to do with fabrication costs, for existing fabs (people wanting to know the costs of their competitors), future fabs (people wanting to know their wafer costs from a new fab). His models are built up from very detailed analysis of things like transistor size or the minimum metal pitch. He doesn't have his own blog, but he occasionally writes posts on SemiWiki. Of course, I recommend SemiWiki in general, but here are just Scotten's posts . To get a flavor of his coverage, try Imec Buried Power Rail and Backside Power Delivery at VLSI . Here's a bit from the middle: Digits to Dollars Digits to Dollars has as its subtitle "Technology Finance & Strategy with Real World Insight". It is written by Jay Goldberg. To give you a flavor, try Can There Be a Long Tail of Semis? Semiconductor Packaging News Despite the name, Semiconductor Packaging News and its daily newsletter cover a lot more than packaging. I suggest subscribing to their daily newsletter (I do). Click on "subscribe" in the top right corner of the website. Munro Live Munro Associates covers everything to do with the manufacture of electric vehicles. A lot of what they do are teardowns, a lot of which they show on their YouTube channel. Their primary business is doing long reports that they sell for $90,000 to automotive companies. Probably, you are not going to buy that. Sometimes they sell summary versions of the report to the general public for $5, which maybe you might. And a summary report does not mean two pages, it is over 100 pages. The summaries are actually prepared as a teaser for potential clients of the full report, which can be over 500 to thousands of pages. These sound expensive but can be cheaper than a company doing its own research. For example, they estimate that to discover the information in their report on electric traction motors would cost over $300,000 just to acquire all the motors, before paying engineers to analyze them. If you look at any of the YouTube channels (there are a lot!) that cover Tesla, none of them have the money or the expertise to buy a Tesla and tear it apart. Instead, they create videos where more than half the content is Munro Live's videos. Right now, Munro are stripping down a Texas-built Model Y, which is the one with the big gigacastings and the structural battery pack of new 4680 batteries. They have not yet got as far as exposing more than the edge of one side of the battery pack. See the thumbnail for the video below. The teardown is going a lot slower than they anticipated. To learn more about this, I suggest that you subscribe to their YouTube channel Munro Live . To give you a flavor of it, here is the latest video as I write this, 4680 Battery Pack: What We Found Under the Foam! https://youtu.be/ozesI3OZEG0 Learn More I suggest you subscribe to at least the free tiers of all the people I wrote about above who have Substacks. Also, if you are interested in automotive, subscribe to Munro Live. I also recommend Asianometry (see my post Asianometry ). And if you haven't already done so, subscribe to my weekly Sunday Brunch email by clicking on...
What Is the Role of the EDA Community in Future Life Science Breakthroughs?
Today's post is about the life-science and EDA panel that took place at the recent Design Automation Conference. For my daily takes written during the conference, see my posts: DAC 2022: Day 1 DAC 2022: Day 2 DAC 2022: Day 3 I originally wrote this post and planned it to run last Monday. But, irony of ironies, it got bumped to this week because I got told about our acquisition of OpenEye Scientific, which we announced that day. The post I wrote then was Cadence Expands into Molecular Simulation with Acquisition of OpenEye Scientific . So already, Cadence is in part of the life-sciences sector. At the end of Anirudh's keynote on day 2 of DAC, he showed the following slide: Some of those topics on the right-hand side of the slide are adjacent to EDA...but not very adjacent. But it turns out that life sciences and biology are more adjacent than you might think. There is already work going on using EDA algorithms in biology, medicine, and brain science. On day 3 of DAC, there was a panel session on just this topic, titled What Is the Role of the EDA Community in Future Life Science Breakthroughs? The quantity of the audience was not large, but the quality was high (me for one!), with several members of the DAC executive committee and a couple of VPs of R&D from companies you know well. I won't name any names since I didn't ask permission. The Panel The panel was (from left to right in the photo): Moderator Apurva Kalia. A few years ago, he made the switch to life science after 30 years working at Cadence and is now a Ph.D. student at Tufts University. Lou Scheffer of Howard Hughes Medical Institute (HHMI). Lou used to be a fellow at Cadence in the digital implementation group before he switched from studying silicon brains to studying real ones. He gave a short talk at DAC 2015, which I covered in my post DAC News, Tuesday . Kate Adamala, Assistant Professor at University of Minnesota. Also co-founder of international synthetic life engineering initiative Build-a-Cell. Sameer Sonkusale, Tufts University, where he is a professor of electrical and computer engineering with appointments in biomedical engineering, and chemical and biological engineering. Rob Aitken. For many years, Rob was at Arm but recently made the switch to Synopsys, where he heads the Office of Technology Strategy. He was also the General Chair of DAC in 2019. Iris Bahar. Not on the panel but in the audience. Organizer of the panel. She is at the Colorado School of Mines, where she heads the CS department. Apurva opened with a couple of slides making a direct comparison between EDA and life sciences: He used these to introduce the two questions he wanted the panel to discuss: Are there knowledge/methods/techniques that can be transferred from EDA into the world of bio/life sciences? How easy/difficult is it to enter the field of bio/life sciences? Introductions Each of the panelists then had a few minutes to give a summary of their position. Lou went first and pointed out that EDA already contributes to life sciences. One example is Rent's rule (which relates the number of I/Os required for a block containing a given number of computing elements). In both cases, EDA and biology, 0.5 to 0.7th power of the number of "gates" gives the number of "pins." He then listed several papers that connect EDA algorithms to life science. Next up was Kate Adamala. She pointed out that nature did not sample all the possible ways to build life. It is really an n=1 situation. Note the image source for the above slide, Charles Darwin. Biology is pretty boring from a chemical point of view. We all use the same ways to build proteins and so on For her, the ultimate challenge is synthetic cells, new cells with new architectures built out of truly interchangeable parts (IP!) in a different chassis. Sameer came next. He had a vision of truly personalized medicine, such as healing wounds with smart bandages and how to overcome the fact that brittle silicon is not a great substrate for putting in the human body. He talked a little about bioinstrumentation, such as analyzing the gut biome not by analyzing *** but by swallowing a pill and tracking it as it analyzes the gastrointestinal tract as it passes through. Finally, it was Rob's turn. He started off doing an inventory of what EDA is good at (see the slide above) Adaptation Use available compute power to boost capacity, performance Compiling circuits into machine code for simulation Map circuits into seas of FPGAs for emulation [or a specialized ASIC in Cadence's case] Simplification Restrict design to enable abstraction Clocked feedback-free digital logic Confine analog behavior Discussion As always, when I try and write down a panel session like this, I precede the questions with "Q," so they stand out. That means they were asked by Apurva. My annotations are in [brackets], meaning that is not something said by the panelists. And this is not a transcript. It is more like how network TV broadcasts the Olympics when it is in a bad timezone as "plausibly live." When questions were asked from the audience, I precede them by "Q Audience." Q: In life sciences, the physics is not well understood. It works well in EDA because the physics is understood. So what kind of modeling can we do? Lou: We can use modeling techniques backwards. We have neurons, we know the synapses, but we don't know the strengths. So we can model it and see if we can get the behavior we observe. Kate: We run into the problem of the physics not being understood all the time. We still don’t know all the components of the cells. It is easier to build bottom-up and see if one day they start to behave like a cell. From there, we can build predictive models. That might or might not work. We haven’t done it yet. Sameer: Models don’t exist because engineers have not really attempted to build them yet. Rob: Look at how EDA was able to be successful. It was the restriction piece. If you can just arbitrarily combine transistors, you end up with a mess. But if you restrict them to CMOS and then build gates and clocks, you get something tractable. We need to pick and abstraction level. You can’t do arbitrary things in chips, but those restrictions don’t exist in biology. Q Audience: What is the equivalent of the standard cell? The models may not be complete, but is there an equivalent? Kate: We don’t even have a satisfactory definition of life, which is a big problem. Rob: If a biological standard cell existed and you could do things with it, we could handle abstraction. Lou: Maybe the reason life succeeds is that it has lots of systems that don’t interact. Q Audience: It looks like EDA + Life Science is a small field [gesturing to the small audience]. Variability, system complexity, reliability. It looks like these are all really difficult for bio-life. So how do we tackle them? Lou: Biology can probably help. Look at circuits behind a fly’s eyes. They are very different. Biology works despite huge amounts of variation, something we might need to learn how to do. Iris: We are dealing with this in the EDA world. We dealt with it many years ago, building reliable computing systems from unreliable components back in the 1940s, and we are dealing with it again now. Lou: Biological systems are amazingly resilient. If you knock out any link, it still works, but maybe not quite as well. If 50,000 gates died in your phone, you’d notice immediately. Q: How do you model biological systems? Kate: Closest is where we watch the progress of a single molecule like ATP [adenosine triphosphate, a key part of Kreb's cycle that delivers all the energy biological cells use]. That’s following molecules rather than following structures. These produce the best results. But when you model neurons, you don’t care at that level. Lou: We can do some high-level modeling. In a synapse, we just treat mitochondria as generating ATP. Rob: Think about how EDA would have evolved if, in 1940, somehow a modern state-of-the-art supercomputer suddenly appeared, and everyone spent decades working out how to build one. Life science is more like that. You have a 3nm chip, and you can’t even see the wires because you need equipment that has not been invented yet. Lou: Synapses we treat as just working, like gate level. Then we have organ level, more like IP. But we need some new models for the biological world. There are 100 chemical products in a synapse, but we can model it simply. Start with SPICE and then move into custom languages for the domain that we are examining. At the high-level we don’t have anything, just Python and MATLAB. Q: How will it be different if we succeed in this collaboration? Lou: Sameer mentioned intelligence in band-aids, but there is no need to restrict them to people who are stuck. Blow your nose, and it tells you what kind of cold you have, or analysis in your toilet. There are far too many stories of people discovered with cancer just because they were X-rayed for a broken wrist or something. Kate: Safety and security. One day we will make biology more efficient, but then it becomes a tool that can be misused. We need to maintain not just our current standard of living but keep ourselves alive through the next pandemic or whatever. We just need to design biology to be better. Sameer: I can see direct impact with designers engaging with life-science and biology, making sensors, and diagnostic tools. More and more people are getting into the field. We will have better models of understanding biology. Issues we haven’t thought of yet. Rob: There are many more nightmare scenarios in life-science than electronics, and we’ve not done a great job of security there. Q Audience: It took billions of years to come up with the [biological] cell. Then we had a Cambrian explosion with lots of creatures. Kate: Once we have a synthetic cell, we can build up complexity in ways we cannot predict for now. Lou: There are lots of chances for this. Every single generation has to work, so you can’t make big changes. If you could design creatures from scratch could build better, like airplanes are faster than birds. Kate: Everything is made from proteins, and ribosomes are not even very good and are terribly slow. Rob: Over time, transistors have got worse since, as you shrink them, they need more power, so a ribosome may be a really bad way of doing it, but perhaps it’s the worst way except for all the other ways. Lou: We don’t know how to build enzymes from scratch. We just copy existing enzymes. So there is lots of room for improvement. Q: How do we do the validation step of any synthetic biology? Lou: There is one big validation step: can you produce children? Kate: If I’m building a strain that makes ethanol, that's the validation step. Biology makes things that make more things. Sameer: We can have a kill switch to turn it off, but can you turn it on again. Creatures cannot reboot. Q: In EDA, we have CS, math, engineering, and so on. In life science, biology and chemistry. How do we get students to be interested in this? Excited about it? Lou: A lot of engineering schools do a sort of survey course in the first year. It seems it should have something like that “life science for engineers” like those "physics for poets" classes. So they can get a feel for whether they are interested. But engineering schools don’t do much in bioscience if any. Q: Four and a half years ago, I decided to switch. Hence going back to school and being in a Ph.D. program. My daughter, a biologist, was one of my teachers. It wasn’t that difficult to switch. Every day is something fascinating. So tell students when they come in about how it can happen. Students don’t realize switching can even happen. Sameer: We need to solve this problem, or we all die long-term. Kate: It would be great if biological students could get exposed to engineering. I have people who haven’t a clue about Python. “Wow, you know how to code," I get told. Rob: Cross-disciplinary activities are really important, even if you never use them. Q: Well, we're out of time, so let's thank the panel. Sign up for Sunday Brunch, the weekly Breakfast Bytes email. .
Coalesce Xcelium Apps to Maximize Performance by 10X and Catch More Bugs
Xcelium Simulator has been in the industry for years and is the leading high-performance simulation platform. As designs are getting more and more complex and verification is taking longer than ever, the need of the hour is plug-and-play apps that are easy to use and can seamlessly fit in the verification environment with minimal changes. Xcelium Apps work natively with the Xcelium Logic Simulator and enable design teams to achieve the highest verification performance at both the IP and full-chip level of modern SoC designs. The Xcelium Machine Learning (ML) App utilizes proprietary ML technology to reduce regression times up to 10X by learning from previous regression runs and guiding the Xcelium randomization kernel to either achieve the same coverage with significantly fewer simulation cycles or catch more bugs around specific coverage points of interest. Xcelium Apps are the next step in the evolution of logic simulation throughput. These apps deliver domain-specific technologies to enable the highest levels of verification performance at both the IP and full-chip level of modern SoC designs. Read below what our customers have to say about the value they saw when they rolled out Apps in their verification flow. Missed reading our press release ? Click here to know more about how you can discover hidden bugs faster and accelerate coverage closure .
Chalk Talks Featuring Cadence
Faster, More Predictable Path to Multi-Chiplet Design Closure
The challenges for 3D IC design are greater than standard chip design - but they are not insurmountable. In this episode of Chalk Talk, Amelia Dalton chats with Vinay Patwardhan from Cadence Design Systems about the variety of challenges faced by 3D IC designers today and how Cadence’s integrated, high-capacity Integrity 3D IC Platform, with its 3D design planning and implementation cockpit, flow manager and co-design capabilities will not only help you with your next 3D IC design.
Enabling Digital Transformation in Electronic Design with Cadence Cloud
With increasing design sizes, complexity of advanced nodes, and faster time to market requirements - design teams are looking for scalability, simplicity, flexibility and agility. In today’s Chalk Talk, Amelia Dalton chats with Mahesh Turaga about the details of Cadence’s end to end cloud portfolio, how you can extend your on-prem environment with the push of a button with Cadence’s new hybrid cloud and Cadence’s Cloud solutions you can help you from design creation to systems design and more.
Machine-Learning Optimized Chip Design -- Cadence Design Systems
New applications and technology are driving demand for even more compute and functionality in the devices we use every day. System on chip (SoC) designs are quickly migrating to new process nodes, and rapidly growing in size and complexity. In this episode of Chalk Talk, Amelia Dalton chats with Rod Metcalfe about how machine learning combined with distributed computing offers new capabilities to automate and scale RTL to GDS chip implementation flows, enabling design teams to support more, and increasingly complex, SoC projects.
Cloud Computing for Electronic Design (Are We There Yet?)
When your project is at crunch time, a shortage of server capacity can bring your schedule to a crawl. But, the rest of the year, having a bunch of extra servers sitting around idle can be extremely expensive. Cloud-based EDA lets you have exactly the compute resources you need, when you need them. In this episode of Chalk Talk, Amelia Dalton chats with Craig Johnson of Cadence Design Systems about Cadence’s cloud-based EDA solutions.
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Learn How Xcelium Apps Help You Achieve Verification Closure Early for IP/SoC Designs
Cadence Xcelium Logic Simulator provides the best engine performance for SystemVerilog, VHDL, SystemC®, e, UVM, mixed-signal, low power, and X-propagation. It leverages a set of domain-specific apps, including mixed-signal, machine learning, functional safety, and more, that enable users to achieve verification closure early for IP and SoC designs. Learn how these domain-specific apps can help you achieve verification closure early for IP and SoC designs.
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See How Lightelligence Created the World’s First Working Optical Computing System
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