The Jasper User Group 2025, the annual must-attend event for the formal community, was hosted on October 29-30 at the Cadence San Jose Headquarters. If you weren't able to join us this year, here is a quick recap: Submissions This year, we received a record number of hig...

Memory interleaving is a technique that distributes memory addresses across multiple memory devices or channels. Instead of storing data sequentially in one device, the system alternates between devices at a fixed granularity. It could help improve bandwidth, reduce latency, ...

Introduction As the industry continues to progress in PCIe, enabling faster and reliable data transfer, with each new generation, PCIe doubles its bandwidth — a change that brings both performance and challenges. When PCIe 6.0 arrived, one critical feature stood out: Forwar...

Great Place To Work ® and Fortune magazine have honored Cadence as one of the Fortune World's Best Workplaces ™ in 2025 , marking the company's tenth appearance on this prestigious list. This global recognition highlights the strength of Cadence's high-p...

The semiconductor industry is advancing at an unprecedented pace, driven by the need for higher performance, greater integration, and maximum efficiency. With Moore's Law slowing, innovative approaches like chiplet-based architectures have taken center stage, especially ...

Intrinsic Semiconductor Technologies, a company transforming the semiconductor industry by bringing fast and efficient non-volatile memory to embedded systems and AI hardware, has achieved a breakthrough in memory verification by adopting the Cadence Spectre FX Simulator. By ...

Securing Innovation As chip design complexity and expectations increase, engineering teams are turning to EDA in the cloud to meet demand, raising another concern: Is your intellectual property safe in the cloud? Cadence's answer is a resounding yes. Through Cadence OnCl...

Serial link speeds have increased 25X in under 20 years, thus increasing the complexity of the IBIS algorithmic modeling interface (AMI) models used in simulating these links. With the increased speed and complexity of designs, it is crucial to analyze channels to ensure suff...

The challenges for 3D IC design are greater than standard chip design - but they are not insurmountable. In this episode of Chalk Talk, Amelia Dalton chats with Vinay Patwardhan from Cadence Design Systems about the variety of challenges faced by 3D IC designers today and how Cadence’s integrated, high-capacity Integrity 3D IC Platform, with its 3D design planning and implementation cockpit, flow manager and co-design capabilities will not only help you with your next 3D IC design.

With increasing design sizes, complexity of advanced nodes, and faster time to market requirements - design teams are looking for scalability, simplicity, flexibility and agility. In today’s Chalk Talk, Amelia Dalton chats with Mahesh Turaga about the details of Cadence’s end to end cloud portfolio, how you can extend your on-prem environment with the push of a button with Cadence’s new hybrid cloud and Cadence’s Cloud solutions you can help you from design creation to systems design and more.

New applications and technology are driving demand for even more compute and functionality in the devices we use every day. System on chip (SoC) designs are quickly migrating to new process nodes, and rapidly growing in size and complexity. In this episode of Chalk Talk, Amelia Dalton chats with Rod Metcalfe about how machine learning combined with distributed computing offers new capabilities to automate and scale RTL to GDS chip implementation flows, enabling design teams to support more, and increasingly complex, SoC projects.

When your project is at crunch time, a shortage of server capacity can bring your schedule to a crawl. But, the rest of the year, having a bunch of extra servers sitting around idle can be extremely expensive. Cloud-based EDA lets you have exactly the compute resources you need, when you need them. In this episode of Chalk Talk, Amelia Dalton chats with Craig Johnson of Cadence Design Systems about Cadence’s cloud-based EDA solutions.

Learn how Switch, a leading designer, builder, and operator of U.S. exascale data centers, is taking their data center’s cooling capabilities even further. In the past 20 years, Switch has built some of the densest air-cooled data center environments. With AI taking off in the last couple of years, see how they were able to deploy many of the first NVIDIA H100 clusters inside using Cadence’s Reality Digital Twin Platform for pre-modeling, design, and validation.facilities.

Deploying data centers with AI high-density workloads and ensuring they are capable for anticipated power trends requires insight. Creating a digital twin using the Cadence Reality Digital Twin Platform helped plan the deployment of current workloads and future-proof the investment. Learn about the collaboration between NV5, NVIDIA, and Cadence to optimize data center efficiency, performance, and reliability. 

Larsen & Toubro built the world’s largest FIFA stadium in Qatar, the world’s tallest statue, and one of the world’s most sophisticated cricket stadiums. Their latest business venture? Designing data centers. Since IT equipment in data centers generates a lot of heat, it’s important to have an efficient and effective cooling system. Learn why, Larsen & Toubro use Cadence Reality DC Design Software for simulation and analysis of the cooling system.

In the AI era, as the signal-data rate increases, the signal integrity challenges in server designs also increase. Wiwynn provides hyperscale data centers with innovative cloud IT infrastructure, bringing the best total cost of ownership (TCO), energy, and energy-itemized IT solutions from the cloud to the edge.