Join our live webinar next Tuesday to learn more about this subject. Introduction Despite the evolution of computer processing capability, improving the efficiency of numerical simulations remains critical. In CFD simulations, the key factor impacting solution quality is meshing. A mesh spacing that does not resolve local variations in the flow variables introduces a discretization error. On the other hand, if the mesh is overly refined, the computational time and effort are needlessly increased. Mesh element types and data structures also impact the human hours and skills required to generate a mesh and the cost per unit of accuracy. Figure 1. Comparison between Local Error-based and Output-based Adaptation Technology. Mesh adaptation (which can be local error-based or output-based), as depicted in Figure 1, is a common technique employed to help improve simulation efficiency. Unstructured mesh adaptation has been used to reduce the mesh size to reach the desired solution accuracy. This technique enables significant improvements in processing time, memory requirements, and storage needed. However, without access to the underlying CAD data, adaptation is limited only to improving off-body grid resolution. While the mesh adaptation technique in Fidelity CFD respects the geometry, improves the mesh quality, adapts to the near-wall shear layers, and reduces run-time for improved CFD solutions. Challenges Usual challenges using mesh adaptation for improved mesh quality are as follows: Adaptation does not resolve the correct geometry. Most adaptation procedures are built into the CFD solver. Hence, they adapt only to a faceted approximation of the actual geometry (i.e., the existing geometry). After adaptation, one has the ideal mesh for the wrong geometry. Adaptation decreases the mesh quality of the locally refined mesh. Many adaptation procedures use a divide-and-conquer approach to enrich the mesh, whereby an existing mesh element is locally divided into additional elements. While convenient to program, this approach can lead to a steady decrease in mesh quality with refinement, reducing the robustness, increasing the run time, and perhaps even increasing the discretization Adaptation in near-wall shear layers where the gradients of the flow variables are extensive has many challenges. Brute force approaches typically use isotropic refinement near walls, causing an explosion in the mesh size. A common strategy to avoid the mesh size explosion employs stretched tetrahedra to resolve the large gradients normal to walls without over­-refining parallel to the wall. However, this approach leads to a massive decrease in mesh quality. Adaptation procedures often lead to excessive run times. This is because the mesh was either over-refined in some direction or location, or the mesh quality decreased during adaptation causing the CFD solver to struggle, or even the simple issue of when to stop the refinement procedure. User Benefits of Fidelity CFD Meshing Fidelity Pointwise is a mesh generation solution that offers ample flexibility in mesh construction techniques and mesh styles. This flexibility is the meshing philosophy of the Fidelity CFD meshing tool and allows it to be applied to a wide range of workflows. The Pointwise mesh adaptation technology separates the meshing and solving steps in a coordinated and automated manner enabling refinement of the mesh as per the developing flow solution or based on the objective of the application (as shown in Figure. 2) Figure 2. Mesh adaptation of a diamond airfoil for two different objectives, i.e., adapted for drag (left) and adapted for shock propagation (right). This automatic mesh refinement tool is used only in those regions where the mesh is deficient. It starts by creating a baseline flow solution, and by using this flow solution, an estimate of the error corresponding to the deficiencies in the mesh size is determined. This step is repeated quite a few times to get a better hold of the mesh discretization error. For high-quality CFD meshing, this method can also be used on off-body voxel meshing for uniform and excellent resolution of the off-body features, specially to capture the wake region. In Figure 3, the wake shear layer mesh for the sedan is refined using the mesh adaption tool. Figure 3. Mesh refinement to define off-body features. Take-Away The Fidelity Pointwise mesh adaptation tool: Adapts to the underlying geometry. Efficiently resolves the mesh within boundary layer regions. Effectively controls the rate of adaptation, successively improving the mesh quality. Reduces run-time To learn more about mesh adaptation in Pointwise, request a free trial license.

I recently talked to Ashish Darbari, the CEO of Axiomise. They are based in London, where Ashish ended up having bounced around the world. But more of that later. I also discovered that he would be presenting at CadenceLIVE In Munich the following week, so I planned to attend that presentation and discuss that in this post too. If you've never heard of Axiomise, let me tell you what they do. They have a four-pronged approach to the market. Ashish explained it to me: Consulting where we can work with companies where employees, including me, can give advice on a limited-time contract. Services angle, we take on the projects in a turnkey manner and code testbenches, etc. These are long-term six months to a year or more. Training: enable people to do it themselves. We have lots of courses, instructor-led, online, video For certain domains like RISC-V companies that don’t have enough talent or budget and want to verify their designs using an automatic solution we have FormalISA. See below in the CadenceLIVE section. Ashish So how did Ashish get to start Axiomise just over five years ago? The first half of his life and education was in India, and he studied to be an electrical engineer. Then he switched to computer science and went to Germany to pursue a master's in computational logic (aka formal methods, in effect). He wanted to find a common ground between electronics and formal. so it seemed hardware model checking would be a perfect topic for a PhD. So he moved to the UK to do a PhD at Oxford (actually, a DPhil. which is Oxford-speak for PhD). Then he went to Intel for six months in Oregon. At the time, 2004, Intel probably had the best formal team in the world, put together after the infamous floating point bug FDIV. If you are interested, see my Semiwiki blog post, Jasper User Group Keynotes , where Bob Bentley tells the story (that was before Cadence had acquired Jasper). After his PhD, which took over five years, he focused more on combining test and formal methods, years before this became a hot topic due to functional safety, at Southampton University for about four years. There were no jobs in the industry in 2010 in formal. But he interviewed with Arm in Cambridge and talked about formal methods. He stayed at Arm for 1.5 years, where, among other things, he created the roadmap for formal verification deployment. He then decided to go "home" to India and worked in a General Motors R&D lab specializing in formal methods applied to control software. But GM had its problems and laid off all the PhDs in Bangalore. So he came back to Britain, got a job at Imagination Technologies, and set up a verification methodology group with three people. They serviced 50 projects in three years, and also trained 90 engineers. But Imagination fell on hard times around then and started to lay people off. His team didn't get laid off, but people left anyway, and he was eventually alone. So he joined OneSpin. But before he moved back to Germany, where they were based, he realized EDA was not his thing, and he was more interested in how the tools were used So he created Axiomise with the goal to "make formal normal". Today they are ten people from across the world based just outside London in Hemel Hempstead. We got to talking about machine learning in Jasper, and he is impressed: I can tell you for the projects we are executing with Jasper, we can see the improvements from machine learning. CadenceLIVE Europe Ashish presented at CadenceLIVE Europe. The first part of his presentation was an introduction to Axiomise, very similar to what I covered in the early part of this post, so I'll skip that. I'll focus on FormalISA (pronounced "formalizer"). This is an automated tool for formal verification of RISC-V processors. It already knows the semantics of all the RISC-V instructions, and so all you need to do is use the GUI to load the processor into the tool and within minutes, hours, or days Jasper will get your proofs of bugs coming out. Sometimes, it is faster than that. One time Ashish set it up, went to boil some water for a cup of tea, and when he got back, it had found many corner-case bugs. There is a GUI to load the processor into the tool, pick a tool, then the design and testbench go inside the formal tool, and within hours or days, you get proofs or bugs coming out. Many processors have been tested in the last few years, and Axiomise found bugs in almost all of them. See the table above for a few. So in the context of RISC-V, Axiomise has a fully-automatic solution. It is actually vendor-neutral, but Ashish says "Jasper is an order of magnitude faster than the other tools." We have not just proofs and bugs but a debugger that extends Jasper and finds the root cause of failure. The diagram above summarizes the capabilities of FormalISA for RISC-V processors. In particular, note that no test cases, manual checkers, or verification code needs to be written. This means that it is not necessary to be a formal verification expert to use FormalISA. As Ashish told me: Some of the testing was done by my son at 13 to make sure it is simple enough. We are taking on the complexity head-on. In the presentation, Ashish ran through a sort of "demo" in slides of FormalISA in action. But it is too many slides to attempt to reproduce here. Of course, if you want a demo, I know Ashish and his team are standing by! Here's one slide to give you a flavor of what the debugger looks like in use. Ashish's last slide summarizes Axiomise's view of the world of formal verification. In particular, formal methods are a necessity, not just nice to have. And for the specific case of RISC-V processors, Axiomise has created a turnkey solution that automates the problem. Cadence and Axiomise In the past, Cadence worked with Oski to provide additional design consulting for customers who needed more help than we could provide with our own AEs. Oski used to have occasional meetings of "Formal Club", sometimes sponsored by Cadence. For example, see my post Decoding Formal Club: Arm and Arteris . But last year, NVIDIA acquired Oski, and so they were unavailable to work with Cadence customers (well, NVIDIA is a Cadence customer, but you know what I mean). Axiomise was already doing similar work since 2018, and now the partnership between Cadence and Axiomise is even stronger and more important. Sign up for Sunday Brunch, the weekly Breakfast Bytes email

Modern electronic designs have many stakeholders involved in the process. It is not uncommon for schematic drawing and pre-design simulation to be done in-house while the layout is handled by a third-party design partner. Allegro ® Pulse not only provides a platform for managing and sharing data between engineers within an organization but also for sharing that data outside of the platform. For example, users may want to leverage Version Control for their layouts, even when shared outside of Allegro Pulse environment for editing. This functionality is available for both Allegro ® PCB Designer board files as well as Allegro ® Package Designer files. The version control process is split into two simple operations, enabled by Allegro Pulse assigning a unique ID to each project it manages: Locking the layout for editing Checking the changes in the layout Locking the Layout for Editing The first step is to lock a layout for editing, sometimes referred to as checking out the file. When working with an Allegro Pulse-managed design, simply right-click the green eye status icon at the bottom-right of the layout editor window and select Lock . An icon instantly appears to signify to other Allegro Pulse users that the design is locked for editing. After it is locked, a .brd or .mcm file can be shared by email, FTP, or by other means with a third-party layout group. Even while outside of the Allegro Pulse environment, the file retains its unique Pulse ID. The third-party layout group can use Save As to rename the layout as needed. Suffixes such as _v1 , _v2 , etc. are common to internally keep track of the layout process. When the layout is shared back for committing into Allegro Pulse, the Pulse ID flags it as a new version of the original shared file and allows it to be committed to Allegro Pulse. Checking in the Changes The second step is to commit, or check in , the changes received. After the third-party layout group is done with their changes, they can simply transfer the file back to the original Allegro Pulse user. When the layout file is opened, Allegro Pulse recognizes it as the same design, and it will still have the lock on the bottom-right of the Allegro layout editor. Committing the Layout into Allegro Pulse The only thing left to do is to commit the layout back into the Allegro Pulse environment. It is recommended to have a clearly defined standard for adding tags and comments when committing to improve traceability of the whole process. The third-party layout partner cannot use their own Allegro Pulse Version Control with the layout. That would overwrite the unique Pulse ID. Aside from this limitation, you can use this method to seamlessly share layout data outside of the Allegro Pulse platform when required. Contact Us For any feedback or any topics you want us to include in our blogs, write to us at pcbbloggers@cadence.com . Do SUBSCRIBE to stay updated about upcoming blogs. About BoardSurfers The BoardSurfers series provides solutions to the various tasks related to the creation and management of PCB design using the Allegro platform products. The name and logo of this series are designed to resonate with the vision of making the design and manufacturing tasks enjoyable, just like surfing the waves. Regular, new blog posts by experts cover every aspect of the PCB design process, such as library management, schematic design, constraint management, stackup design, placement, routing, artwork, verification, and much more.

It's a new week in CFD and time to refresh our memories about what's going on here at Cadence Fidelity CFD. From The Blogs Cadence and McLaren Accelerate Innovation During a recent visit to the Cadence office in Austin, Texas, McLaren CEO Zak Brown discussed the Cadence-McLaren partnership and the importance of Cadence Fidelity CFD in their Formula 1 race cars. Read more . I’m Samuel Afari and This Is How I Mesh The latest installment in our This Is How I Mesh series (in which we introduce you to someone from our Fidelity CFD team or to someone anywhere in the world of CFD) you'll meet Samuel Afari, a Ph.D. student at Embry-Riddle and an Applications Engineer intern here at Cadence. Read more . Giving EV Batteries a Second Life With the roads flooded with electric vehicles worldwide, it is on us to give EV batteries a second life, which would count as an effort to reduce e-waste and achieve the net zero emission targets set by policymakers. Read more Smooth Extrusion for Accurate Viscous Flow Simulation An optimization-based smoothing technique in Fidelity Pointwise promises to accurately resolve the boundary layers in a viscous flow by extruding a mix of prisms and hexahedra. Read more . This Week in CFD Our 490th edition of This Week in CFD pulls together some of the latest news in CFD, CAD, CAE, HPC, and many other acronyms. Read more . Events Generate the Best Mesh Every Time - Automatically, 13 Dec Unstructured meshing can automate much of the mesh generation process, saving significant engineering time and cost. However, controlling numerical errors resulting from the discrete mesh requires adaptation to the developing solution. Join this webinar to learn how Cadence CFD mesh adaptation methods use a continuous-size field that gets updated as the solution progresses. As a result, adherence to the underlying CAD geometry is maintained, and mesh quality is ensured. Register today . HiFiLeD Symposium, 14-16 Dec Join us in Brussels for this in-person event. The HiFiLed Symposium will be focusing on all aspects related to these objectives, ranging from issues concerning the complexity, reliability, accuracy, and uncertainties in generating the High-Fidelity LES/DNS data to their application towards turbulence and transition modelling. It will include progress on the underlying high-order numerical methods (HOMs), innovative approaches for CPU acceleration for LES and DNS, exploitation of massive parallel architectures, efficient post-processing on massive parallel hardware, innovative machine learning methods, as well as experimental data. Register today . AIAA SciTech, 23-27 Jan AIAA SciTech Forum is the world’s largest event for aerospace research, development, and technology. This year’s forum will be held at the Gaylord National Resort & Convention Center in Nation Harbor, Maryland, just outside Washington, DC. Cadence will have staff at the conference presenting papers in technical sessions, demonstrating software, and answering technical questions at our booth #511. Read more . CadenceLIVE Silicon Valley 2023, 19-20 Apr Mark your calendars and plan to attend CadenceLIVE Silicon Valley next 19-20 April in the Santa Clara Convention Center. This will be the place to interact with the Fidelity CFD team, share best practices with other Fidelity CFD customers, and learn about what the future holds for Fidelity CFD. We invite you to present your work with Fidelity CFD, and your abstract is due by 31 January. Read more . Videos Michigan Electric Boat Propels the Naval Industry with Cadence CFD Tools, Including Fine Marine The University of Michigan’s electric boat racing team, Michigan Electric Boat, is propelling the next generation of the naval industry forward with Cadence CFD tools, including Fine Marine. They’re designing, building, and racing electric boats to compete on a national stage, and they’ve committed themselves to innovation. Learn more about their mission to decarbonize the industry and get the world closer to net zero carbon emissions. Watch now . Fidelity Pointwise - Entity Selection Tools Mastering the software's tools for selecting entities in the geometry model and mesh will improve your workflow. Watch now . Using the Admin Tool to Set Up Your Fidelity CFD License We continue our series of videos on how to install and use Fidelity CFD. Learn how to quickly download, deploy, and use the Admin Tool to activate your license file or to connect to a license server. Watch now .

Electronic design automation (EDA) has been experiencing a renaissance of sorts, breaking new ground in broader markets that focus on the computational (mathematical/data-driven) aspects of intelligent system design. While the industry has long played an essential role in semiconductor design, new requirements and skills are required for system analysis, integration, multi-core computing, and artificial intelligence—largely driven by the massive amounts of data and the need to perform multi-physics analysis of the entire system. For more than 30 years, Cadence has partnered closely with our customers to create amazing technologies that enable the vast array of electronic devices we rely on every day. Our sphere of influence is broad, encompassing a host of markets including consumer, hyperscale computing, mobile, communications, automotive, aerospace, industrial, and healthcare. We attribute our success to our laser-sharp customer focus, creativity, collaboration, and teamwork, our ability to explore what’s possible, and our quality execution that drives results for even the most demanding customers. Behind these successful engagements are many decades of valuable life and work experience, much of it gained working side by side with our customers to address their most pressing design challenges. As the industry continues to evolve and become increasingly specialized and complex, attracting bright new talent is imperative. At this critical juncture, there’s no better time to encourage more young women to embark on a STEM career. The semiconductor and systems ecosystem, and EDA in particular, is a great place for them to make their mark. We can only benefit from the perspective and skills women bring to the table. In EMEA, and in the UK specifically, there aren’t enough women pursuing science and engineering degrees at the university level. According to the Engineering UK 2018 report, as interpreted by the Women’s Engineering Society (WES), only 25.4% of girls aged 16-18 would consider a career in engineering, compared to 51.9% of boys. Girls and women comprise less than 18% of higher apprentices in engineering and manufacturing, and 7.4% of all engineering apprentices. Yet in all STEM A-Levels except chemistry, more girls get A-C grades than boys. Girls’ lack of interest and representation in the engineering ranks can be attributed to educational and societal factors. While pre-teens might initially express interest in STEM, a 2017 Microsoft study found these girls’ interest waned for a variety of reasons, including a shortage of female role models in STEM, lack of practical, hands-on experience, and a shortage of teachers that talk about STEM. The study found that role models and support both at home and in the classroom were key to sustaining girls’ interest in STEM subjects. It’s clear the way STEM is taught at school needs to change but undertaking such a shift is a monumental task. Engineering itself should be promoted as a profession since there is often ambiguity about the role of an accredited engineer, and we must encourage greater diversity in all spheres of engineering. In the UK, enticing more women to join the engineering ranks has become a priority. Girls need more relatable role models in the popular press, as well as support and encouragement at home. We must help these young women explore what’s possible and envision all they can do with a STEM degree. Reflecting our complex world today, career advice should be holistic and encompass more than just traditional roles. For instance, there are a variety of career paths one can pursue with a physics degree besides being a physicist. As the industry continues to evolve and become increasingly specialized and complex, attracting bright new talent is imperative. My own career trajectory is a good example. I graduated from university with a Bachelor of Science degree in business information technology, which was essentially a software development degree with a small commercial business element. I wasn’t interested in being a software developer, but my education provided a good base to spring from. I thought I wanted to do product marketing. My career grew from there, and I ended up in sales. Women may realize they have an aspiration to do something, only to later find out they may not do it well or even enjoy it. And that’s okay! Once women decide to embark on a STEM career, they need both male and female executive sponsors to help them grow their careers and climb the ladder. Early in my career, I was fortunate enough to have a male mentor whose support played a critical role in my career development. Upon graduating from university, I started out doing marketing and PR at a small research lab that was a spinout of EMI Music. It wasn’t a core strength and I didn’t enjoy it. Then I started doing business development with the CEO, who was my champion. He recognized where I excelled and wanted to find the right job for me. I was really good at talking to customers and contributed to the first wins in the company’s early days. His support early on was very important in my career development. I worked with him later at another company, and we’re still very close 20 years later. In addition to encouraging more women to embark on STEM careers and fostering their career growth, we also need to attract new talent into EDA—regardless of gender. Software engineering graduates coming out of university today naturally gravitate toward systems companies like Google and Facebook. Cadence and the rest of our ecosystem historically have had difficulty competing to recruit this new talent because most graduates don’t fully understand the vital role we play. Until recently, our industry wasn’t viewed as modern, exciting, and edgy, but it truly is! Collectively we have some of the brightest minds in the world enabling exciting new technologies that are not only making major contributions to society but also influencing how we interact with the world in our everyday lives. With more industry talent contemplating retirement in the next decade, it’s crucial that we create a larger pool of qualified candidates. Recruiting new talent to the industry and fostering more female technical talent are both key to this effort. It’s time for the entire ecosystem—Cadence, our competitors, partners, and customers—to unite to address this challenge. For the continued health and growth of this vital industry and the customers we serve, we need to work together.

CadenceLIVE Europe took place on Monday and Tuesday at the start of Thanksgiving week in Munich, Germany. It was in-person for the first time in three years. There were about 550 people there, maximum capacity. As in the past, the first day starts at lunchtime on Monday to give people time to fly in from other parts of Europe. Then, CadenceLIVE kicked off with keynotes. Tom Beckley, Cadence Tom Beckley opened up the conference with his keynote. Tom has a very wide portfolio of products, including PCB, packaging, RF, system analysis, custom and analog design, and more. He started by looking at the challenges and opportunities facing the semiconductor industry as we approach the start of 2023: Moore's Law is not dead, and "more than Moore" is perhaps the hottest area in semiconductors right now There is a global shortage of semiconductors, especially in automotive Increasing electrification of automotive, aerospace and defense, consumer, and industrial markets Systems companies are building their own silicon There is a worldwide scarcity of engineering talent Everyone's got a CHIPS act: foundry capital investment plus government subsidies to improve supply chain resilience AI innovation The semiconductor market is forecast to grow 50% in the next decade GlobalFoundries is out of capacity through the end of 2023 Tom moved on to give a brief tutorial on the October 7th announcement by The Department of Commerce’s Bureau of Industry and Security (which apparently was not discussed with the Department of Defense and caught them by surprise). Most of the rest of Tom's talk was about various recent product announcements. Since I covered all of those when we made the announcements, I won't repeat everything here. Tom wrapped up by teasing everyone with a preview of some results from future AI enablement in PCB and IC Packaging that we will be announcing in 2023. For example, the above PCB took 59 hours to route after a manual placement. Using AI-driven placement and routing, the board was routed in 20 minutes and had 16% better wirelength. When we officially announce this capability next year, I will cover it here on Breakfast Bytes. Oliver Wolst, Bosch The industry keynote was given by Dr. Oliver Wolst of Bosch Semiconductors. He started out with a few slides on Bosch's operations all over the world. They have over 36 manufacturing sites in 17 countries and have capabilities for semiconductor design of CMOS, RF-CMOS, analog, mixed-signal, MEMS, and power. He was especially pleased that in 2017, Bosch had decided to build a 300mm wafer fab in Dresden, three years before the start of the semiconductor shortage. He said that they often manufacture the same part at foundries and in-house, which has helped during the shortage by giving them flexibility. He wrapped up that section: You’ve made it through the advertising block. So let’s talk about change. He discussed how there is going to be a change in architecture to a service-oriented architecture...but today all in-vehicle communication is signal-based. All automotive OEMs will introduce new digital business models…about ten years after Tesla did it. Only a centralized architecture can hold the software complexity, and most of the OEMs (car companies) have developed such an architecture to be introduced in 2026+, but there are issues: All these architectures across all brands are much too costly. Also, scalability has not been achieved. Why has that failed? His view is that there are two reasons. The first is technology consistency of functional blocks for functions that are distributed, and the second is there is a collaboration model between different companies that is new and has yet to grow. In the past, systems were designed by the tier-1s (like Bosch). Now we are moving to what he calls IDM+, a semiconductor maker with a semiconductor business but also a system business. There are new requirements for hardware-software co-design. Bosch is convinced that they need to build a model of the entire hardware for running the full software stack. But they need to avoid adding additional compute at every level, or the whole stack will be anything but lean. Of course, the foundation for this type of development is the dynamic duo, Palladium Zx and Protium Xx (where x is 1 or 2). One example took two months to bring up in Protium, then a few more months to add SpeedBridge, and they could communicate with real Ethernet test equipment. Everyone is unhappy with the current state of central computing. There is lots of complaining and the integration costs are spinning out of control. Despite this, all the OEMs are going to have a central architecture in 2025 to 2026. By 2029, about half the vehicles on the planet will have a centralized architecture. Other challenges are that there is not enough PCB space for all the chips. The power consumption is completely unacceptable. Efficient scalability is not there at all. Not to mention time-to-market. In HPC, the trend is to chiplets (see lots of Breakfast Bytes posts on just this topic). This might be a solution to these issues. However, the R&D cost is much too high for the automotive market to shoulder on its own. Oliver had a chiplet wishlist. Reading between the lines, the automotive industry is betting on a supply of COTS chiplets developed for other purposes but that they can then reuse in automotive. This requires a change in approach: A market of multiple suppliers contributing chiplets, rather than a captive business model doing it all in one stack. Need system-level planning and top-down thinking. But it is a frightening number of chiplets, so we are working on how to reduce these numbers. How to scale with the least possible number of chiplets. And how to use non-automotive chiplets, too. Finally, he came to what he called "the most important slide of the day" about the Open SoC Ecosystem for Automotive (see above). Today we see two companies addressing this in its entirety. Must have synergy with non-automotive market since the automotive market alone is too small to recover the investment. For level 3 and level 4 driving, we do not see any components that are meeting the requirements since the dataflow in these SoCs is not what is needed. So that the task is not covered. In addition, these companies will not offer a scalable portfolio since it is an additional cost that can’t be borne. I'm guessing he is referring to Qualcomm and NVIDIA since they are the only companies addressing the whole stack. Of course, Tesla is doing its own stack, but that doesn't help other OEMs. The chiplet is not just the technology, it is a trend that would allow new kinds of cooperative business models, synergies that are definitely required. Captive business models, that was yesterday. That is how Bosch will proceed going forward. Technical Sessions The rest of the day (and the following day) were taken up by multiple parallel tracks: Automotive and IP Solutions Digital Design and Signoff Verification PCB and Multiphysics Systems RF, RF Systems, and Packaging Cloud Custom and Analog Design Mixed Signal Design Academic I attended a selection of these sessions, which I will write blog posts about during the rest of the year. A Fireside Chat Monday evening finished with a social/networking hour in the expo hall, followed by dinner in the big ballroom where the keynotes had taken place. In between, there was a "fireside chat" in which Rebecca Dobson, corporate VP of WFO for Europe, interviewed some guy called Paul McLellan. We talked about trends in the semiconductor industry, most notably automotive, since Robert Schweiger and I had a new automotive book that we were giving away. For details on the book, see my post, Books: Hyperscale and Automotive . Sign up for Sunday Brunch, the weekly Breakfast Bytes email

Cadence® Perspec System Verifier is a portable stimulus, system-on-chip (SoC) verification solution. The Perspec System Verifier improves SoC quality and saves time by reducing development effort for defining complex SoC-level use cases and amplifying use case exploration of state space and timing on fast platforms. It also helps to create coverage-driven automation of system use-case generation, bridging UVM and SoC verification methodology and shrinking the time required to reproduce, debug, and fix complex SoC-level bugs. Compared to manual test development, you’ll be able to generate 10X more tests 10X faster using this platform solution. The Perspec system verifier is based on Portable Stimulus Standard (PSS), the Accellera system initiative standard. The Portable Test and Stimulus Standard defines a specification for creating a single representation of stimulus and test scenarios usable by a variety of users across different levels of integration under different configurations. It enables the generation of different implementations of a scenario that run on a variety of execution platforms, including, but not necessarily limited to, simulation, emulation, FPGA prototyping, and post-silicon. With this standard, users can specify a set of behaviors once, from which multiple implementations may be derived. The latest course is based on PSS 2.0 specification and Perspec 22.03 version. The course covers many topics, including: PSS Scenario Modeling Mapping model to implementation code Scenario Creation Functional Coverage The course starts with an introduction and shortcomings of the existing verification solutions and delves into how PSS addresses them. Then it introduces PSS modeling techniques along with its key constructs. It also introduces the Perspec System Verifier flow and explains how the tool implements PSS using an example Design under test (DUT). After an introduction, it gives more details about various components in the Perspec verification flow along with labs. The “Capturing Scenario Model” module covers modeling concepts that use PSS constructs like components, actions, and data types. It also explains flow and resource objects, their mapping to the scenario model and PSS data types, and constraint modeling. The “Mapping model to implementation code” module explains various mapping techniques for realizing a scenario model to target language. It introduces different types of “exec” blocks and compares/contrasts between native execs and target language templates usages. The “Scenario Creation” module explains how a scenario is composed by a user in Perspec and how it’s analyzed to give out the solution. It explains the graphical user interface (GUI) of the Perspec tool, along with functionalities in various GUI panes. It also contains an example covering the whole flow for better understanding. Last, it contains the concepts used for functional coverage and how to analyze it using the Perspec tool. The course is available here on the Cadence support page: There is also a Digital Badge available. Perspec System Verifier - Basic v22.03 (Badge Exam) For questions and inquiries, or issues with registration, reach out to us at Cadence Training . Want to stay up to date on webinars and courses? Subscribe to Cadence Training emails. To view our complete training offers, visit the Cadence Training website . Cadence® Perspec System Verifier is a portable stimulus, system-on-chip (SoC) verification solution. The Perspec System Verifier improves SoC quality and saves time by reducing development effort for defining complex SoC-level use cases and amplifying use case exploration of state space and timing on fast platforms. It also helps to create coverage-driven automation of system use-case generation, bridging UVM and SoC verification methodology and shrinking the time required to reproduce, debug, and fix complex SoC-level bugs.

A mesh that resolves the boundary layer is an absolute necessity for accurate simulation of viscous flow. Resolution in this context implies to A sufficient number of cells to capture the gradients across the boundary layer A smooth variation in cell-to-cell size ratio across the boundary layer A sufficiently small near-wall spacing, Orthogonality of the transverse grid lines to the walls, and Well-shaped cells. Here, the resolution largely depends on the applied meshing technique. An optimization-based smoothing technique in Fidelity Pointwise promises to accurately resolve the boundary layers in a viscous flow by extruding a mix of prisms and hexahedra. Smoothing in Hybrid Meshes Fidelity Pointwise has two techniques for generating hybrid meshes: traditional algebraic extrusion and anisotropic tetrahedral extrusion, also known as T-Rex . Both techniques start from a tri or quad mesh and march outward, creating layers of cells (prisms and hexahedra, respectively). T-Rex is an advancing layer technique that marches each grid point on the extrusion front outward in a nominally orthogonal direction to the wall and with step sizes prescribed to achieve the proper boundary layer resolution. The anisotropic tetrahedra produced by joining each extruded point back to the extrusion front are combined to form stacks of prisms or hexahedra. T-Rex includes extensive smoothing methods to control the extrusion trajectory, adjust cell shapes, and avoid collisions with other extrusion fronts. Algebraic extrusion in Fidelity Pointwise consists of defined trajectories for the mesh to follow, including extrusion along a line, rotation around an axis, along a user-prescribed path, and normal to the initial mesh. A variety of smoothing options is necessary to ensure that the algebraic techniques generate a non-folded mesh simply because they lack an elegant mathematical basis like the PDE methods. Optimization-based Smoothing Technique Introducing mixed-cell grids in Fidelity Pointwise requires smoothing in the extrusion methods to account for cell-to-cell variation. In addition to supporting mixed cell types in the same grid, the new smoothing aims to optimize element shape and size to ensure good boundary layer resolution. To smooth extrusions from a front consisting of both triangles and quads (i.e., extruding prisms and hexahedra side by side), the perturbation of each node on the advanced layer must be smoothed to account for competing effects of different cell types. Applying Extrusion and Smoothing Onera M-6 The ONERA M-6 wing is a slightly swept, low aspect ratio wing with a rounded tip and sharp trailing edge. A surface mesh consisting of zones of quads (for leading and trailing edge resolution) and triangles is shown in Figure 1. Algebraic extrusion using the standard method was applied with a first step height of 0.0001 and a step size growth rate of 10 percent per step. Figure 1. Close-up view of a hybrid mesh near the tip of the ONERA M-6 wing. Forty layers were extruded using 50 smoothing iterations per step for both P=0 and P=2. Views of the symmetry plane regions at the wing root of the extruded grids are shown in Figure 2. The wiggles for the P=0 case (left) result from biasing the smoothing to the worst cost function, which in this case, is the enforcement of the symmetry plane condition. The P=2 case (right) grid is smoother because it is biased toward the average cost function. Figure 2. 40 extrusion layers on the symmetry plane of the ONERA-M6 wing at the leading edge for smoothing exponent P=0 (left) and P=2 (right). The Eglin Pylon The finned pylon from the Eglin mutual interference experiment was meshed with all triangles and prisms extruded to test the new smoothing method's ability to handle convex regions such as the fin-body junction. The outer extrusion fronts after 25 steps for 100 smoothing sweeps with smoothing exponent P set to 0, 1, and 2 are shown in figure 3. The P=2 case (bottom) indicated nine prisms with inverted corners in the region near the fin trailing edge, while the P=0 and P=1 cases identified no problem elements. This is due to the lower exponents biasing toward repair of the worst cost function. Figure 3. 25th extrusion layer for prism extrusion off the Eglin pylon/store for smoothing exponent P=0 (left), P=1 (middle), and P=2 (right). To try Fidelity Pointwise to extrude smooth boundary layer meshes for your viscous CFD applications, click the button below –

The challenges for 3D IC design are greater than standard chip design - but they are not insurmountable. In this episode of Chalk Talk, Amelia Dalton chats with Vinay Patwardhan from Cadence Design Systems about the variety of challenges faced by 3D IC designers today and how Cadence’s integrated, high-capacity Integrity 3D IC Platform, with its 3D design planning and implementation cockpit, flow manager and co-design capabilities will not only help you with your next 3D IC design.

With increasing design sizes, complexity of advanced nodes, and faster time to market requirements - design teams are looking for scalability, simplicity, flexibility and agility. In today’s Chalk Talk, Amelia Dalton chats with Mahesh Turaga about the details of Cadence’s end to end cloud portfolio, how you can extend your on-prem environment with the push of a button with Cadence’s new hybrid cloud and Cadence’s Cloud solutions you can help you from design creation to systems design and more.

New applications and technology are driving demand for even more compute and functionality in the devices we use every day. System on chip (SoC) designs are quickly migrating to new process nodes, and rapidly growing in size and complexity. In this episode of Chalk Talk, Amelia Dalton chats with Rod Metcalfe about how machine learning combined with distributed computing offers new capabilities to automate and scale RTL to GDS chip implementation flows, enabling design teams to support more, and increasingly complex, SoC projects.

When your project is at crunch time, a shortage of server capacity can bring your schedule to a crawl. But, the rest of the year, having a bunch of extra servers sitting around idle can be extremely expensive. Cloud-based EDA lets you have exactly the compute resources you need, when you need them. In this episode of Chalk Talk, Amelia Dalton chats with Craig Johnson of Cadence Design Systems about Cadence’s cloud-based EDA solutions.

Long gone are the days where engineers imported text-based reports into spreadsheets and sorted the columns to extract useful information. Introducing the Cadence Joint Enterprise Data and AI (JedAI) platform created from the ground up for EDA data such as waveforms, workflows, RTL netlists, and more. Using Cadence JedAI, engineering teams can visualize the data and trends and implement practical design strategies across the entire SoC design for improved productivity and quality of results.

Is design closure taking too long? Introducing the Cadence Certus Closure Solution, a revolutionary new tool that optimizes and delivers overnight design closure for both the chip and subsystem. Learn how the solution supports the largest chip design projects with unlimited capacity while substantially improving productivity by up to 10X.

About two-thirds of the world’s population lacks access to medical imaging, whether in developing nations or in first-world countries with underserved communities. Driven by a vision of improving the standard of healthcare around the world, Butterfly Network designs and makes the first 3D Ultrasound imaging system and whole-body imager that's small enough to be carried in your pocket.

Optimize your verification workload, boost coverage, and accelerate root cause analysis to reduce silicon bugs and accelerate your time to market with Cadence Verisium AI-Driven Verification. Learn how this generational shift from single-run, single-engine algorithms to algorithms leverages big data and AI across multiple runs of multiple engines throughout an entire SoC verification campaign.