fish fry
Subscribe Now

Verification for You and Me! DVCon U.S. 2022 and The New Cadence Midas Safety Platform

Design verification is the name of the game of this week’s Fish Fry podcast. First up, John Dickol (DVCon 2022 U.S. Program Chair) and I chat about this year’s DVCon Virtual Conference, the new two stage paper submission process for this year’s conference and what you can expect by attending. Also this week, Robert Schweiger (Cadence) joins me to discuss why standardization is crucial to functional safety design today and the details of Cadence’s new comprehensive safety solution for faster certification of automotive and industrial designs.

 

 

Click here to download this episode

 

Links for February 11, 2022

Register for DVCon U.S. 2022

DVCon U.S. 2022 Advance Program Available: Keynote to focus on Artificial Intelligence & Machine Learning

DVCon U.S. 2022 To Offer Interactive Virtual Program: Addition of Gather.Town designed to enhance networking experience for all participants

Cadence Introduces Comprehensive Safety Solution for Faster Certification of Automotive and Industrial Designs

 

 

Click here to check out the Fish Fry Archive.

Click here to subscribe to Fish Fry via Podbean

Click here to get the Fish Fry RSS Feed

Click here to subscribe to Fish Fry via Apple Podcasts.

Click here to subscribe to Fish Fry via Spotify

 

Fish Fry Executive Interviews

Anupam Bakshi, CEO – Agnisys

Dave Kleidermacher, CTO – Green Hills Software

Robert Blake, CEO – Achronix

Jack Harding, CEO – eSilicon

Michiel Ligthart, COO – Verific

Adnan Hamid, CEO – Breker Technologies

Simon Davidmann, CEO – Imperas

Jessica Gomez – Rogue Valley Microdevices

Shishpal Rawat, Chairman – Accellera Systems Initiative

Kevin Bromber, CEO – myDevices

Daniel Hansson, CEO – Verifyter

Mark Papermaster, CTO – AMD

David Fried, CTO – Coventor

Dr. Steven LeBoeuf, President – Valencell

David Dutton, CEO – Silvaco

Bob Niemiec, CEO – TwistThink

Allan Martinson, COO – Starship Technologies

Zhihong Liu, Chairman and CEO – ProPlus Solutions

Taher Madraswala, CEO and President – Open-Silicon

Kapil Shankar, CEO and Director – AnDAPT

Dan Fox, CTO – Local Motors

Kim Rowe, Founder and CEO — RoweBots

Lawrence Cooke, Founder and CEO — NovaSolix

Gregg Recupero, CTO — Performance-IP

Alan Grau, CEO — Icon Labs

Carl Alberty, Vice President – Cirrus Logic

Maximilian Odendahl, CEO — Silexica

Finbarr Moynihan, General Manager — MediaTek

Sanjay Pillay, CEO — Austemper

Louis Parks, CEO – SecureRF

Harold Blomquist, CEO – Helix Semiconductor

Dale Dougherty and Sherry Huss, Co-Founders – Maker Faire

David Su, CEO – Atomic Technologies

Mung Chiang, EVP and Dean of Engineering College – Purdue University

Clay Johnson, CEO – CacheQ

Andy Hock, Vice President, Product – Cerebras Systems

Dan Goehl, Co-founder and Chief Business Officer – UltraSense Systems

Charlie Green, Chief Operating & Technical Officer – Powercast

 

 

Leave a Reply

featured blogs
Dec 2, 2024
The Wi-SUN Smart City Living Lab Challenge names the winners with Farmer's Voice, a voice command app for agriculture use, taking first place. Read the blog....
Nov 22, 2024
I just saw a video on YouTube'”it's a few very funny minutes from a show by an engineer who transitioned into being a comedian...

featured video

Introducing FPGAi – Innovations Unlocked by AI-enabled FPGAs

Sponsored by Intel

Altera Innovators Day presentation by Ilya Ganusov showing the advantages of FPGAs for implementing AI-based Systems. See additional videos on AI and other Altera Innovators Day in Altera’s YouTube channel playlists.

Learn more about FPGAs for Artificial Intelligence here

featured paper

Quantized Neural Networks for FPGA Inference

Sponsored by Intel

Implementing a low precision network in FPGA hardware for efficient inferencing provides numerous advantages when it comes to meeting demanding specifications. The increased flexibility allows optimization of throughput, overall power consumption, resource usage, device size, TOPs/watt, and deterministic latency. These are important benefits where scaling and efficiency are inherent requirements of the application.

Click to read more

featured chalk talk

Shift Left Block/Chip Design with Calibre
In this episode of Chalk Talk, Amelia Dalton and David Abercrombie from Siemens EDA explore the multitude of benefits that shifting left with Calibre can bring to chip and block design. They investigate how Calibre can impact DRC verification, early design error debug, and optimize the configuration and management of multiple jobs for run time improvement.
Jun 18, 2024
42,035 views