fish fry
Subscribe Now

Papa’s Got a Brand New Node: Intel Makes Waves in Process and Packaging

On your mark. Get set. Let’s fry some fish! In this week’s podcast, I chat with Sanjay Natarajan (Senior Vice President and Co-General Manager, Logic Technology Development at Intel) about what the roadmaps for Intel’s process and packaging technologies looks like, the motivations behind Intel’s move to a new node naming convention, and what Sanjay believes will be the key factors that will drive the continuation and success of Moore’s Law. Also this week, I check out how new research from the University of Tsukuba is improving the possibility of launching rockets using a high-power beam of microwave radiation.

 

Click here to download this episode

Links for August 13, 2021

Intel Accelerates Process and Packaging Innovations

‘Intel Accelerated’ Webcast

Accelerating Process Innovation (Fact Sheet)

Intel’s Path to Manufacturing Leadership (Blog)

Microwave-Powered Rocket Propulsion Gets a Boost (University of Tsukuba)

 

 

Leave a Reply

featured blogs
Dec 7, 2023
Building on the success of previous years, the 2024 edition of the DATE (Design, Automation and Test in Europe) conference will once again include the Young People Programme. The largest electronic design automation (EDA) conference in Europe, DATE will be held on 25-27 March...
Dec 7, 2023
Explore the different memory technologies at the heart of AI SoC memory architecture and learn about the advantages of SRAM, ReRAM, MRAM, and beyond.The post The Importance of Memory Architecture for AI SoCs appeared first on Chip Design....
Nov 6, 2023
Suffice it to say that everyone and everything in these images was shot in-camera underwater, and that the results truly are haunting....

featured video

Dramatically Improve PPA and Productivity with Generative AI

Sponsored by Cadence Design Systems

Discover how you can quickly optimize flows for many blocks concurrently and use that knowledge for your next design. The Cadence Cerebrus Intelligent Chip Explorer is a revolutionary, AI-driven, automated approach to chip design flow optimization. Block engineers specify the design goals, and generative AI features within Cadence Cerebrus Explorer will intelligently optimize the design to meet the power, performance, and area (PPA) goals in a completely automated way.

Click here for more information

featured paper

Power and Performance Analysis of FIR Filters and FFTs on Intel Agilex® 7 FPGAs

Sponsored by Intel

Learn about the Future of Intel Programmable Solutions Group at intel.com/leap. The power and performance efficiency of digital signal processing (DSP) workloads play a significant role in the evolution of modern-day technology. Compare benchmarks of finite impulse response (FIR) filters and fast Fourier transform (FFT) designs on Intel Agilex® 7 FPGAs to publicly available results from AMD’s Versal* FPGAs and artificial intelligence engines.

Read more

featured chalk talk

The Next Generation of Switching Regulator
Sponsored by Mouser Electronics and RECOM
Power modules can bring a variety of benefits to electronic system design including reduced board space, shorter time to market and easier sourcing of materials. In this episode of Chalk Talk, Amelia Dalton and Louis Bouche from RECOM discuss the benefits of RECOM’s switching regulators, the details of their advanced 3D power packaging and how you can leverage RECOM’s expertise with your next design.
Jan 9, 2023
39,445 views