EEJournal

fish fry
Subscribe Now
September 27, 2019

Get Smart(er)!

Reinventing Analog IP, Edge Native Infrastructure, and Making Our Smart Systems Even Smarter
by Amelia Dalton

Work smart. Get things done. – Susan Wojcicki

What’s smarter than smart? This week’s episode of Amelia’s Weekly Fish Fry! Tim Ramsdale (CEO – Agile Analog) reveals how Agile Analog is changing the landscape of analog IP and why their unique design methodology sets their analog IP away from the rest of the pack. In our second interview this week, Tom Yates (Product VP – Nubix.io) joins us to discuss the current state of edge computing and how is Nubix.io helping embedded designers get the most out of their IoT and edge-based designs.

 

Click here to download this episode

 

Click here to check out the Fish Fry Archive.

Click here to subscribe to Fish Fry via Podbean

Click here to get the Fish Fry RSS Feed

Click here to subscribe to Fish Fry via iTunes.

 

Fish Fry Executive Interviews

Anupam Bakshi, CEO – Agnisys

Dave Kleidermacher, CTO – Green Hills Software

Robert Blake, CEO – Achronix

Jack Harding, CEO – eSilicon

Michiel Ligthart, COO – Verific

Adnan Hamid, CEO – Breker Technologies

Simon Davidmann, CEO – Imperas

Ted Miracco, CEO – SmartFlow Compliance Solutions

Jessica Gomez – Rogue Valley Microdevices

Shishpal Rawat, Chairman – Accellera Systems Initiative

Kevin Bromber, CEO – myDevices

Daniel Hansson, CEO – Verifyter

Mark Papermaster, CTO – AMD

David Fried, CTO – Coventor

Dr. Steven LeBoeuf, President – Valencell

David Dutton, CEO – Silvaco

Bob Niemiec, CEO – TwistThink

Allan Martinson, COO – Starship Technologies

Zhihong Liu, Chairman and CEO – ProPlus Solutions

Taher Madraswala, CEO and President – Open-Silicon

Kapil Shankar, CEO and Director – AnDAPT

Dan Fox, CTO – Local Motors

Lawrence Cooke, Founder and CEO — NovaSolix

Gregg Recupero, CTO — Performance-IP

Alan Grau, CEO — Icon Labs

Carl Alberty, Vice President – Cirrus Logic

Maximilian Odendahl, CEO — Silexica

Finbarr Moynihan, General Manager — MediaTek

Sanjay Pillay, CEO — Austemper

Louis Parks, CEO – SecureRF

Harold Blomquist, CEO – Helix Semiconductor

Dale Dougherty and Sherry Huss, Co-Founders – Maker Faire

Mike Wisart, CEO – efabless

Chris Giovanniello, SVP and Co-Founder – Menlo Micro

Jake Janovetz, President – Opal Kelly

Jerry Gipper, Executive Director – VITA

Ethan Plotkin, CEO – GDCA

Xin Song, CEO – Bottos

Chris Dries, CEO – UnitedSiC 

Bob Smith, Executive Director – ESD Alliance 

Rick O’Connor, Executive Director – RISC V Foundation

Naveed Sherwani, CEO and Yunsup Lee, CTO/Founder- SiFIve

Doug Letcher, CEO and President – Metrics Technologies

Jun Pei, CEO – Cepton Technologies

Nikos Zervas, CEO – CAST

Dave Hughes, CEO – HCC Embedded

David Su, CEO – Atomic Technologies

Jess Isquith, President/CEO – PICMG

Galen Hunt, Distinguished Engineer and Managing Director, Microsoft Azure Sphere – Microsoft 

Vinay Gokhale, VP Business Development – ThirdWayv

Kevin Hannah, Director of Product Operations- Kazuhm

Srinath Anantharaman, CEO – ClioSoft

Leave a Reply

featured blogs
Wave Generation Revisited and Other Highlights of Fine Marine v11.1
Oct 5, 2022
The newest version of Fine Marine - Cadence's CFD software specifically designed for Marine Engineers and Naval Architects - is out now. Discover re-conceptualized wave generation, drastically expanding the range of waves and the accuracy of the modeling and advanced pos...
More from Cadence...
6 Reasons to Leverage IC Hardware Development in the Cloud
Oct 4, 2022
We share 6 key advantages of cloud-based IC hardware design tools, including enhanced scalability, security, and access to AI-enabled EDA tools. The post 6 Reasons to Leverage IC Hardware Development in the Cloud appeared first on From Silicon To Software....
More from Synopsys...
What’s It All About, Alfie?
Sep 30, 2022
When I wrote my book 'Bebop to the Boolean Boogie,' it was certainly not my intention to lead 6-year-old boys astray....
More from Max's Cool Beans...

featured video

PCIe Gen5 x16 Running on the Achronix VectorPath Accelerator Card

Sponsored by Achronix

In this demo, Achronix engineers show the VectorPath Accelerator Card successfully linking up to a PCIe Gen5 x16 host and write data to and read data from GDDR6 memory. The VectorPath accelerator card featuring the Speedster7t FPGA is one of the first FPGAs that can natively support this interface within its PCIe subsystem. Speedster7t FPGAs offer a revolutionary new architecture that Achronix developed to address the highest performance data acceleration challenges.

Click here for more information about the VectorPath Accelerator Card

featured paper

Algorithm Verification with FPGAs and ASICs

Sponsored by MathWorks

Developing new FPGA and ASIC designs involves implementing new algorithms, which presents challenges for verification for algorithm developers, hardware designers, and verification engineers. This eBook explores different aspects of hardware design verification and how you can use MATLAB and Simulink to reduce development effort and improve the quality of end products.

Click here to read more

featured chalk talk

Enabling Digital Transformation in Electronic Design with Cadence Cloud

Sponsored by Cadence Design Systems

With increasing design sizes, complexity of advanced nodes, and faster time to market requirements - design teams are looking for scalability, simplicity, flexibility and agility. In today’s Chalk Talk, Amelia Dalton chats with Mahesh Turaga about the details of Cadence’s end to end cloud portfolio, how you can extend your on-prem environment with the push of a button with Cadence’s new hybrid cloud and Cadence’s Cloud solutions you can help you from design creation to systems design and more.

Click here for more information about Cadence Cloud Portfolio