fish fry
Subscribe Now

Let’s Get Speedy! Digital Signal Processing for Always-On Systems, Sensor Fusion and Computer Vision

What would a Friday be without a deep dive into digital signal processing for computer vision and AI? In this week’s Fish Fry podcast, Pulin Desai (Cadence Design Systems) joins me to discuss the need for increased speed in computer vision algorithms today, the unique processing requirements for sensor fusion, 3D capture, always-on systems, and the details of Cadence’s new Vision Q8 and Vision P1 DSPs. Also this week, I take a closer look at a new research study at the University of Gothenburg that contends that machine learning may be the key to finding effective testing methods during epidemic outbreaks.

 

 

Click here to download this episode

Links for June 18, 2021

More information about Vision Q8 DSP

More information about Vision P1 DSP

Introducing our latest Vision AI IP: Tensilica Vision Q8 & P1 DSP (Video)

Tensilica Vision Q8 and P1 DSPs, More AND Less (Blog)

Click here to check out the Fish Fry Archive.

Click here to subscribe to Fish Fry via Podbean

Click here to get the Fish Fry RSS Feed

Click here to subscribe to Fish Fry via Apple Podcasts.

Click here to subscribe to Fish Fry via Spotify

 

Fish Fry Executive Interviews

Anupam Bakshi, CEO – Agnisys

Dave Kleidermacher, CTO – Green Hills Software

Robert Blake, CEO – Achronix

Jack Harding, CEO – eSilicon

Michiel Ligthart, COO – Verific

Adnan Hamid, CEO – Breker Technologies

Simon Davidmann, CEO – Imperas

Jessica Gomez – Rogue Valley Microdevices

Shishpal Rawat, Chairman – Accellera Systems Initiative

Kevin Bromber, CEO – myDevices

Daniel Hansson, CEO – Verifyter

Mark Papermaster, CTO – AMD

David Fried, CTO – Coventor

Dr. Steven LeBoeuf, President – Valencell

David Dutton, CEO – Silvaco

Bob Niemiec, CEO – TwistThink

Allan Martinson, COO – Starship Technologies

Zhihong Liu, Chairman and CEO – ProPlus Solutions

Taher Madraswala, CEO and President – Open-Silicon

Kapil Shankar, CEO and Director – AnDAPT

Dan Fox, CTO – Local Motors

Kim Rowe, Founder and CEO — RoweBots

Lawrence Cooke, Founder and CEO — NovaSolix

Gregg Recupero, CTO — Performance-IP

Alan Grau, CEO — Icon Labs

Carl Alberty, Vice President – Cirrus Logic

Maximilian Odendahl, CEO — Silexica

Finbarr Moynihan, General Manager — MediaTek

Sanjay Pillay, CEO — Austemper

Louis Parks, CEO – SecureRF

Harold Blomquist, CEO – Helix Semiconductor

Dale Dougherty and Sherry Huss, Co-Founders – Maker Faire

David Su, CEO – Atomic Technologies

Leave a Reply

featured blogs
Dec 5, 2023
Generative AI has become a buzzword in 2023 with the explosive proliferation of ChatGPT and large language models (LLMs). This brought about a debate about which is trained on the largest number of parameters. It also expanded awareness of the broader training of models for s...
Nov 27, 2023
See how we're harnessing generative AI throughout our suite of EDA tools with Synopsys.AI Copilot, the world's first GenAI capability for chip design.The post Meet Synopsys.ai Copilot, Industry's First GenAI Capability for Chip Design appeared first on Chip Design....
Nov 6, 2023
Suffice it to say that everyone and everything in these images was shot in-camera underwater, and that the results truly are haunting....

featured video

Dramatically Improve PPA and Productivity with Generative AI

Sponsored by Cadence Design Systems

Discover how you can quickly optimize flows for many blocks concurrently and use that knowledge for your next design. The Cadence Cerebrus Intelligent Chip Explorer is a revolutionary, AI-driven, automated approach to chip design flow optimization. Block engineers specify the design goals, and generative AI features within Cadence Cerebrus Explorer will intelligently optimize the design to meet the power, performance, and area (PPA) goals in a completely automated way.

Click here for more information

featured paper

Power and Performance Analysis of FIR Filters and FFTs on Intel Agilex® 7 FPGAs

Sponsored by Intel

Learn about the Future of Intel Programmable Solutions Group at intel.com/leap. The power and performance efficiency of digital signal processing (DSP) workloads play a significant role in the evolution of modern-day technology. Compare benchmarks of finite impulse response (FIR) filters and fast Fourier transform (FFT) designs on Intel Agilex® 7 FPGAs to publicly available results from AMD’s Versal* FPGAs and artificial intelligence engines.

Read more

featured chalk talk

Using the Vishay IHLE® to Mitigate Radiated EMI
Sponsored by Mouser Electronics and Vishay
EMI mitigation is an important design concern for a lot of different electronic systems designs. In this episode of Chalk Talk, Amelia Dalton and Tim Shafer from Vishay explore how Vishay’s IHLE power inductors can reduce radiated EMI. They also examine how the composition of these inductors can support the mitigation of EMI and how you can get started using Vishay’s IHLE® High Current Inductors in your next design.
Dec 4, 2023
285 views