This One Goes to 58!

Xilinx Ups the SerDes Ante

by Kevin Morris

The scope display clearly showed 58.0 Gbps. I was curious. I was expecting a 56 gig demo - you know, the next official step in the traditional “doubling of the data rate” that we get with each process node in FPGA transceivers. The last node sported 28Gbps SerDes transceivers, so, clearly, this time we should be dealing with 56. I started to ask about the discrepancy, but somehow I knew the answer already:

“Yeah, but this one goes to 58!”  Read More


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bmoyer
What do you think about how DSA fits into the design flow?

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or
foreach (*0) {*0

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