What You Call EDA, I Call IP

EDA Past, Present, and Future with Lucio Lanza

by Amelia Dalton

He's toiled at this project for years - dreamt about it, laid awake at night thinking about it, and even built a lab in his basement to test it. Eventually he brought in friends (from work mostly) to fill in the missing pieces, and before he knew it they really had something. We all know this story. It has played out time and time again. It's the story of the startup, and today's Fish Fry celebrates the men and women who work every day with innovation in their hearts and minds. My distinguished guest is Lucio Lanza, an EDA mentor, venture capitalist, and believer in startup innovation. Lucio is here to explain why funding startups is so crucial in today's EE ecosystem and where he thinks EDA is headed in the future. Also this week, we check out a brand new way to get that semiconductor quote you've been looking for without giving you a headache or breaking your fax machine.  Read More


latest news

December 18, 2014

Real Intent Joins IEEE P2415™ Unified Hardware Abstraction and Layer Working Group

December 17, 2014

GLOBALFOUNDRIES and Cadence Deliver First SoC Enablement Solution Featuring ARM Cortex-A17 Processor in 28nm-SLP Process

Altium Announces Expanded Benefits to Subscription Customers

Synopsys' PrimeTime ADV Achieves Rapid Adoption for Fastest Timing Closure

New ASSET InterTech eBook explains how QPI self-healing bus can hinder circuit board quality

December 16, 2014

Library Expert Enhanced Support for Altium Designer

Synopsys and Imec Expand TCAD Collaboration to 5 nm and Beyond

December 15, 2014

Synopsys Surpasses Milestone of 100 VC Apps on the Verdi Debug Solution

December 12, 2014

Saelig Launches GDS-200 and GDS-300 Compact/Portable Digital Oscilloscopes

December 11, 2014

Cadence Perspec System Verifier Delivers Up to 10X Productivity Improvement in System-on-Chip Verification

PLS’ Universal Debug Engine (UDE) now also supports the Infineon TLE986x and TLE987x Embedded Power ICs

December 10, 2014

Coverity Scan Report Shows Big Data Projects Reducing Defects to Take on Internet of Things

December 09, 2014

Synopsys' New LPDDR4 Verification IP Accelerates Verification Closure for High-Performance Low Power Designs

December 08, 2014

Synopsys' Latest Release of IC Compiler II Ready for Broad Availability of the Power of 10X

Latest Release of Synopsys' LightTools Delivers Advanced Features for Illumination Design

EDA News Archive

New Synopsys SoC Test Features

Cell-Aware: Meet Slack-Based. And STAR: Meet eFlash.

by Bryon Moyer

Single-Electron Transistors

A Whole New Way of Switching

by Bryon Moyer

Plan 8 from Outer Space

Calypto’s Catapult 8 Takes Us Higher

by Amelia Dalton

Xilinx Divides the World

Separate Flows Target Software and Hardware

by Kevin Morris

Spaghetti versus ISO 26262

Are You Ready for Tomorrow?

by Dick Selwood

EDA Article Archive

 

Editors' Blog

Beefed-Up Sensor Subsystem

posted by Bryon Moyer

Synopsys has updated the DesignWare subsystem that they debuted last year. (17-Dec)

On the Scene: Almost-Instant Semi Quotes with eSilicon

posted by Amelia Dalton

Good night red tape. Online Semi quotes made easy with eSilicon (8-Dec)

Verdi: Not Just for Debug Anymore

posted by Bryon Moyer

Synopsys is leveraging Verdi for things that aren’t debug. Like verification planning. (25-Nov)

If This Is a Conference, then It Must Be November

posted by Bryon Moyer

A quick look at some of the events I’ll be attending over the next few weeks. (24-Oct)

Faster Extraction from Cadence

posted by Bryon Moyer

Cadence has upgraded their parasitic extraction tools for the 16-nm node. (28-Aug)

EDA Editors' Blog Archive

forum

I Am tRoot

Posted on 12/18/14 at 6:23 AM by RyanKenny

RyanKenny
Or 'Better Living Through Digital Signatures'

How to create mushroom designs on an oscilloscope signal detector using sound

Posted on 12/18/14 at 4:06 AM by HhindieR

Supply and demand go hand in hand. Where demand exists, supply will meet it. Some people demand they have dinosaur fossils, which leads to the interesting underworld of fossil smuggling. One of the more significant examples in recent memory is the case of…

Encapsulating Engineering

Posted on 12/18/14 at 1:29 AM by Kev

Not sure it's a good analogy (the "road" thing). The way we write software (C/C++) is very dependent on how the machines work, so there's a lot of interdependency that shouldn't be there in the "stack". The "top" of the current stack is reminding me of ho…

EDA Forum Archive

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On Demand

Three Ways that Allegro TimingVision Environment Speeds Up Timing Closure of High-Speed PCB Interfaces

Addressing the Advantages of Embedded LTE and Advanced LTE

OrCAD Constraint Driven Design Flow

Design Data Management with PTC Windchill and Cadence Allegro PCB

A Methodology for High-Speed Nanometer Transceiver Verification, Validation, and Characterization

A Complete Analog Design Flow for Verification Planning and Requirement Tracking

The Vault

What is Electrically Aware Design?

Increase FPGA Performance with Enhanced Capabilities of Synplify Pro & Premier

Physically Aware Synthesis Techniques to Lower Power, Improve Timing, Congestion & Correlation

Abstract and Conquer: A New Alternative to Hierarchical Timing Analysis

Signoff-Driven Timing Closure ECO in the Synopsys Galaxy Platform

PADS VX: Redefining Productivity

Integrating Electronic Design Analysis Upstream, Downstream, and Sideways

Vivado In-System Debug

Design Control, Data & Comparison with PADS Design Archive

Protium Rapid Prototyping Platform

Static Timing Analysis and Constraint Validation

Announcing ProtoCompiler for Multi-FPGA Prototyping

Scripted Flows in Vivado Design Suite

Vivado Design Suite: Integrated Design Environment

Rigid-Flex and Embedded Components

Verify Design Performance with PADS Best-in-Class Simulation and Analysis

EDA On Demand Archive


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