Xilinx Throws Down

Unveils New 16nm UltraScale+ Families

by Kevin Morris

When the #1 FPGA company makes what is arguably their biggest new-technology announcement in a decade, you’d expect there to be a lot of substance. With this week’s announcement of UltraScale+ Virtex, Kintex, and Zynq devices planned to roll out on TSMC’s 16nm FinFET process, the company did not disappoint. This is one of the broadest, most complex announcements we have ever heard from Xilinx. So, with that preface, let’s take a look at what those folks on the south side of San Jose have been up to lately.

In summary, Xilinx is announcing new Virtex, Kintex, and Zynq families of programmable devices with major improvements in capability over previous generations.  Read More

latest news

February 26, 2015

Altium announces new release of the TASKING C compiler for Renesas RH850

February 25, 2015

Altium Announces Tasking C Compiler for the Next Generation Bosch GTM-IP MCS

February 24, 2015

Keysight Technologies Introduces Infiniium V-Series Oscilloscopes for Greater Insights in Validation, Debug

Digi-Key Expands Mentor Graphics’ EDA Tools Portfolio with New Features & Low-Priced Premium Bundles

Cadence Announces Stratus High-Level Synthesis Platform

Altium Announces Updates to Flagship High-Speed PCB Design Tool

February 23, 2015

Express Logic Launches ViewX™ System Analyzer to Speed Optimization of IoT Applications

February 20, 2015

Digi-Key to Showcase EDA Tools via Hands-On Demos at Embedded World 2015

February 16, 2015

Mentor Graphics Signs Agreement with CADD Edge to Distribute Electronic Design and Analysis Products

February 11, 2015

Synopsys' New DesignWare DDR Explorer Tool Delivers Up to 20 Percent Improvement in DDR Memory Subsystem Efficiency

Accellera Systems Initiative Forms Portable Stimulus Working Group

February 03, 2015

ARM and Cadence Provide Energy-Efficient, Comprehensive Media Components for Mobile Market

Synopsys' New 25G/50G Ethernet Verification IP Enables Next-Generation Gigabit Designs

February 02, 2015

Register for DVCon 2015 Today!

January 29, 2015

Synopsys' New DesignWare Medium Density NVM IP Family Reduces Die Cost by Up to 25 Percent

EDA News Archive

Soup to Nuts

Design Verification’s Party of the Year and Supply Chain Risks We Should Avoid

by Amelia Dalton

Achronix Beats the Odds

Full Production on High-Performance FPGAs and Tools

by Kevin Morris

Build Your Own EDA Tool

Without Competing With the Big Guys

by Bryon Moyer

Engineering Childhood’s End

Radio Shack Goes From 50-in-1 to None

by Kevin Morris

MathWorks Targets Hardware/Software

Prototyping MATLAB and Simulink Algorithms on Xilinx Zynq and Altera SoCs

by Eric Cigan, FPGA/SoC Technical Marketing, MathWorks

EDA Article Archive


Editors' Blog

What Does a 5-nm Transistor Look Like?

posted by Bryon Moyer

Imec and Synopsys announced TCAD collaboration at 5 nm. What mischief could they be up to? (17-Feb)

Is Someone Tampering with Your IoT?

posted by Bryon Moyer

You may take comfort in encrypting your stored data and securing your communications and authenticating anyone coming through the front door. But are there ways you haven’t thought about in which your system is being corrupted? If you don’t know about these ways, by definition, then how can you be sure? (5-Feb)

Calypto Refreshes HLS

posted by Bryon Moyer

Catapult 8 helps bridge the transition from RTL-level design to HLS-level design. (14-Jan)

BSIMProPlus Gets a Makeover

posted by Bryon Moyer

ProPlus has revamped their flagship simulation tool, unifying the environment and giving it a new coat of GUI. (7-Jan)

Beefed-Up Sensor Subsystem

posted by Bryon Moyer

Synopsys has updated the DesignWare subsystem that they debuted last year. (17-Dec)

EDA Editors' Blog Archive


Xilinx Throws Down

Posted on 02/26/15 at 12:46 PM by TotallyLost

@gobeavs -- and it wasn't that many years ago that key Xilix staff were brutally vocal putting down folks pioneering C/SystemC to RTL.

Now the company stand is: Vivado HLS accelerates design implementation and verification by enabling C, C++, and Syst…

Xilinx Throws Down

Posted on 02/26/15 at 10:43 AM by kevin

@gobeavs, I'm as impressed with this announcement as anybody, but I think you're assigning a bit too much nobility to Xilinx and Altera marketing when you say "I don't think Xilinx or Altera put some lame effective LUTs... number out there."

Let's rev…

Xilinx Throws Down

Posted on 02/25/15 at 2:15 PM by gobeavs

Just another nail in the coffin for Achronix. I think it's funny that Achronix puts a LUT count on the hard IP. That is an interesting marketing ploy. I don't think Xilinx or Altera put some lame effective LUTs including hard IP number out there.

You k…

EDA Forum Archive

subscribe to our eda newsletter

On Demand

Saving Routing Resources, Speeding Up Timing Closure at Freescale Semiconductor

How Real Number Modeling Improves Functional Verification for Mixed-Signal SoCs

Mixed Signal Verification: The Long and Winding Road

Debug This! Class-based testbench debugging with Visualizer

Optimizing Emulator Utilization

Sigrity PowerSI Tackles SSO Noise: Customer Success Story

What’s New in OrCAD PCB Editor 16.6

Solution for Heterogeneous Multicore Embedded Systems

The Vault

What is Electrically Aware Design?

Increase FPGA Performance with Enhanced Capabilities of Synplify Pro & Premier

Physically Aware Synthesis Techniques to Lower Power, Improve Timing, Congestion & Correlation

Abstract and Conquer: A New Alternative to Hierarchical Timing Analysis

PADS VX: Redefining Productivity

Integrating Electronic Design Analysis Upstream, Downstream, and Sideways

Vivado In-System Debug

Design Control, Data & Comparison with PADS Design Archive

Protium Rapid Prototyping Platform

Static Timing Analysis and Constraint Validation

Scripted Flows in Vivado Design Suite

EDA On Demand Archive

Login Required

In order to view this resource, you must log in to our site. Please sign in now.

If you don't already have an acount with us, registering is free and quick. Register now.

Sign In    Register