Over the FR4 and Through the Woods

To Grandma's PCB We Go

by Amelia Dalton

This week’s Fish Fry is all about your next PCB design. From power integrity to mixed-signal place and route, from Gerber files to schematics, from output pins over the FR4 and through the vias, to grandma’s house we go. My first guest this week is Greg Lebsack from Tanner EDA, and we discuss why you want a digital place and route tool, integrating ye ol’ analog into your next design, and what Tanner EDA brings to the mixed-signal party. Next up, we bring in Hemant Shah from Cadence Design Systems to chat about one of the biggest pain points of PCB design: the hand off to manufacturing. Hemant and I investigate a rapidly expanding industry consortium that is hoping to change all of that awful file hand off once and for all.  Read More


latest news

November 19, 2014

Synopsys Expands IP Accelerated Initiative with New DesignWare IP Prototyping Kits for 10 Interface Protocols

November 18, 2014

Oticon Standardizes on Synopsys' Design Compiler Graphical

November 17, 2014

Synopsys' IC Validator Adopted by Plastic Logic for Physical Verification of Advanced Displays

November 12, 2014

Plunify’s InTime Design Optimization Software Supports Altera FPGAs and SoCs

Tektronix Releases First Test Solution for MIPI M-PHY® Specification v3.1

Altium and element14 Partner to Distribute New PCB Design Tool CircuitStudio

November 11, 2014

Nitero Achieves First-Pass Silicon Success for Industry's First Mobile 60GHz SoC Using Synopsys DesignWare IP for PCI Express and Tools

November 10, 2014

Sonics Adopts Cadence JasperGold Apps Formal Verification for On-Chip Network IP Development

Latest Release of Synopsys' CODE V Optimizes Optical Design Performance for Cost-Effective Manufacturing

Digi-Key Expands Portfolio of EDA Software Tools

November 07, 2014

ProPlus Design Solutions Strengthens Leadership Position with Re-Innovated, Long-Lived BSIMProPlus SPICE Modeling Platform

November 06, 2014

Keysight Technologies Introduces Oscilloscope Probes for High-Voltage Signal Measurements

Mirabilis Design joins the RapidIO.org and announces VisualSim RapidIO Modeling Library: A system-level model of the RapidIO 10xN standard for rapid architecture exploration of computing, defense and networking systems.

November 05, 2014

Altera and MathWorks Deliver Unified Model-Based Design Workflow for Altera SoCs

November 04, 2014

MetaEdit+ 5.1 brings rich graphical DSLs for collaborative development

EDA News Archive

Constraining Light

Or, How the Heck Do I Design a Photonic Circuit?

by Bryon Moyer

First Responder Robots and Virtual Prototypes

Carbon’s New Virtual Prototype Portal and UDG’s New Smart Robot

by Amelia Dalton

Expanding EDA

Newer Tools Let You Do More than Just Electronics

by Bryon Moyer

Shifting Left

Designing Code, Breaking Code, and the Verification in Between

by Amelia Dalton

Go-Fast FPGA Design

Helpful Hot-Rodding Hints

by Kevin Morris

EDA Article Archive

 

Editors' Blog

If This Is a Conference, then It Must Be November

posted by Bryon Moyer

A quick look at some of the events I’ll be attending over the next few weeks. (24-Oct)

Faster Extraction from Cadence

posted by Bryon Moyer

Cadence has upgraded their parasitic extraction tools for the 16-nm node. (28-Aug)

Planning PCB, Package, and Die Together

posted by Bryon Moyer

Cadence’s OrbitIO tries to tie together disparate tools and inefficient ways of planning pinouts. (31-Jul)

Intelligent VIP

posted by Bryon Moyer

Arrow Devices focuses on building semantics into their VIP for a higher level of abstraction. (23-Jul)

Improved FPGA Tool Results

posted by Bryon Moyer

Plunify tries to get the best out of FPGA design tools (21-Jul)

EDA Editors' Blog Archive

forum

A Sale of Thirty-Two Bitties

Posted on 11/19/14 at 3:08 PM by WEATHERBEE

My suggestion: Dump the uncompetitive x86 and commodity ARM plans and focus on GPGPU and high-performance computing.

A Sale of Thirty-Two Bitties

Posted on 11/19/14 at 2:09 PM by TotallyLost

TotallyLost
I've done a couple server designs around Intel Xeon products, and while general documentation is easy to access with NDA, unless there are serious sales numbers behind the design, it's difficult to get additional support or docs.

AMD has been even a bi…

Build Your Own RTOS in 30 Minutes

Posted on 11/19/14 at 12:41 PM by ericverhulst

Just from SynthOS website:
- "Interrupts are supported. System used forced cooperation for multitasking rather than pre-emption."
Then look at the figures for interrupt latency, context switch time, etc.
=> pretty slow compared to any other embedded RT…

EDA Forum Archive

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On Demand

Power-Aware Verification in Mixed-Signal Simulation

Assertion-Based Emulation Using Veloce

SoC Interconnect Verification

The Vault

OrCAD Now! Signal Integrity Presentation

OrCAD Now – PSpice

TripleCheck VIP

How to Debug Double Patterning results using Calibre RealTime

How to select specific rule checks for a Calibre DRC run

Speed IP Bring-up and SoC Validation with HAPS-DX

Synopsys ProtoCompiler for RTL Debug with HAPS Systems

What is Electrically Aware Design?

Increase FPGA Performance with Enhanced Capabilities of Synplify Pro & Premier

Physically Aware Synthesis Techniques to Lower Power, Improve Timing, Congestion & Correlation

Abstract and Conquer: A New Alternative to Hierarchical Timing Analysis

PADS VX: Redefining Productivity

Integrating Electronic Design Analysis Upstream, Downstream, and Sideways

Vivado In-System Debug

Design Control, Data & Comparison with PADS Design Archive

Protium Rapid Prototyping Platform

Static Timing Analysis and Constraint Validation

Scripted Flows in Vivado Design Suite

Vivado Design Suite: Integrated Design Environment

Rigid-Flex and Embedded Components

Verify Design Performance with PADS Best-in-Class Simulation and Analysis

Maximize Your Power and Efficiency with PADS Interactive Placement and Routing

Cadence Low Power Solution - RTL to GDSII Low Power Design

Routing Interfaces Quickly & Efficiently on PCBs

EDA On Demand Archive


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