Expanding EDA

Newer Tools Let You Do More than Just Electronics

by Bryon Moyer

Welcome to autumn. It’s usually a busy season – although the activity typically starts more with the onset of September and the resumption of school than with the equinox. But it also comes on the heels of a quiet season, even in the overworked US.

And EDA has seemed moderately quiet. So I started looking around to see what I might have been missing, and I’m not sure there’s a lot. But it did get me musing on why things might be quiet for the moment as well as what fills the gap – which gets to the topic of what qualifies as EDA. It’s more than you might think.

At the risk of being obviously over-simple, the legions of coders in EDA-land are doing one of two things: building new technologies or improving on old ones. The new technology category might include support for FinFETs or multi-patterning or the design kits for the latest silicon node. The improvement side of the tree is where performance and capacity and usability are juiced up – all in the name of productivity, of course.  Read More


latest news

October 01, 2014

Synopsys' Galaxy Design Platform Delivers Over 30% Leakage Power Reduction for Fujitsu Semiconductor's ARM-Powered Multi-Core

Altium broadens ARM Cortex-M device support to its TASKING C compiler for ARM

September 30, 2014

TSMC and Synopsys Accelerate Custom Design Productivity for 16FF+ Process

Synopsys Announces New Additions to Liberty to Significantly Speed up Timing Closure

ATopTech’s Physical Implementation Tools Certified to Support Advanced Designs in TSMC’s 16nm FinFET+ Process

September 29, 2014

Coverity Launches Code Spotter™ in Free Beta Version to Speed Defect Detection in Java Code

Cadence IP Portfolio and Tools to Support New TSMC Ultra-Low Power Technology Platform

ARM and Synopsys Expand Collaboration to Improve Quality of Results and Time-to-Results for Leading-Edge ARMv8-A and ARMv7-A Cores

Cadence and ARM Expand System-on-Chip Design Collaboration with New Multi-Year Technology Access Agreement

September 26, 2014

Cadence Digital and Custom/Analog Tools Achieve TSMC Certification for 16FF+ Process

September 25, 2014

Zuse Institute Berlin reduces debugging time on enterprise software research projects with UndoDB

Saelig Introduces Device For Safety Measuring High Voltage Power Transistors with Oscilloscopes

New development system includes real-time hardware debug, industrial Ethernet and Fieldbus capabilities

Synopsys Tools Achieve TSMC Certification for 16-nm FinFET+ Process and Entered 10-nm FinFET Collaboration

September 23, 2014

Synopsys Unveils Verification Continuum to Enable Next Wave of Industry Innovation in Software Bring-Up for Complex SoCs

EDA News Archive

Shifting Left

Designing Code, Breaking Code, and the Verification in Between

by Amelia Dalton

Go-Fast FPGA Design

Helpful Hot-Rodding Hints

by Kevin Morris

Going Vertical

Ecosystem for Interposer-based Design?

by Kevin Morris

On The Hunt: Part One

HLS and Sub-atomic Particle Jitter

by Amelia Dalton

Optimization Moves Up a Level

Mentor’s RealTime Designer Rises to RTL

by Bryon Moyer

EDA Article Archive

 

Editors' Blog

Faster Extraction from Cadence

posted by Bryon Moyer

Cadence has upgraded their parasitic extraction tools for the 16-nm node. (28-Aug)

Planning PCB, Package, and Die Together

posted by Bryon Moyer

Cadence’s OrbitIO tries to tie together disparate tools and inefficient ways of planning pinouts. (31-Jul)

Intelligent VIP

posted by Bryon Moyer

Arrow Devices focuses on building semantics into their VIP for a higher level of abstraction. (23-Jul)

Improved FPGA Tool Results

posted by Bryon Moyer

Plunify tries to get the best out of FPGA design tools (21-Jul)

Synopsys’s IP Initiative

posted by Bryon Moyer

Synopsys is taking a holistic view of SoC design using IP, including hardware and software elements. (17-Jun)

EDA Editors' Blog Archive

forum

Expanding EDA

Posted on 10/01/14 at 10:32 AM by bmoyer

bmoyer
Fortunately, I chose a suitably imprecise measure by conjuring up "legions." So I can safely say "yes." smiling

Max 10 Kills the CPLD

Posted on 10/01/14 at 9:28 AM by kevin

kevin
Ouch! Marketing filter... I am shamed. I thought I was a little snarky even, a couple of places. In my defense, the dead CPLD part was completely original. I have always thought it funny that there is a whole class of FPGAs that we still pretend are CPLDs…

Max 10 Kills the CPLD

Posted on 10/01/14 at 3:12 AM by juergenuk

juergenuk
@Steve DevKits are mostly subsidized, so does not count. I meant designed in, product cost, how does it compare Altera - Lattice - Microsemi - Xilinx imlementation ( sorry if I forgot some ). I know there are many variants - any example/volume appreciat…

EDA Forum Archive

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