Tools for the Gifted
Packet Plus Brings Debugging to Networking Engineers
Networking engineers are some of the best and brightest among us. There are good reasons for this. Designing networking equipment is a demanding discipline, spanning a wide gamut of areas from analog and signal integrity to digital design to software - and integrating all of these elements at something near their maximum performance potential. In order to get a competitive piece of network hardware out the door, you are literally designing at the bleeding edge of everything. Read More
latest news
February 03, 2012
February 02, 2012
Allinea adds spark to debugging with Allinea DDT 3.1
SiSoft and IBM Present Paper on Advanced IBIS-AMI Modeling Techniques
February 01, 2012
Symtavision to showcase new versions of SymTA/S and TraceAnalyzer at Embedded World 2012
Agilent Technologies Introduces Precision Waveform Analyzer Module with Industry-Best Performance
EMA Automates the Creation and Setup of OrCAD Capture CIS Component Databases
January 30, 2012
Altium collaborates with Altera to release new online component resources and software support
SiSoft Presents Tutorial on IBIS-AMI Model Quality
January 27, 2012
Agilent Technologies Introduces Industry’s First Reference Clock Multiplier for Receiver Test
ACE announces ABI testing in Rembrandt Release of the SuperTest compiler test and validation suite
January 26, 2012
Agilent Technologies Introduces Add-In Extensions for Compliance Application Software
The Valley of FPGA
Where Green Pastures End
It Has to Get Better
A Look Back at 2011
Editors' Blog
MEMS Tool Upgrade
posted by Bryon Moyer
Design tools for MEMS are very different from design tools for circuits – simply because you’re solving mechanical problems. Yesterday, Coventor announced some upgrades to their MEMS design tools. (1-Feb)
Describing User-Defined Faults
posted by Bryon Moyer
The Cell-Aware fault modeling approach allows ad hoc faults to be identified, but how do you communicate those faults to the test-generation tools? Especially if you have some faults you want to define by hand? (28-Nov)
Power Contributors
posted by Bryon Moyer
Unlike delay, it’s looking like the various contributors to circuit power can be disentangled, simplifying modeling work. (1-Nov)
Bridging Digital and Custom Domains
posted by Bryon Moyer
Synopsys makes it easier to work in both domains. That is, without making it so easy that there’s only one domain… (17-Oct)
Yield Correlations Get Continued Focus
posted by Bryon Moyer
ITC happened a couple weeks ago, and that’s when lots of test- and yield-related announcements come out of hibernation. Improving yield was a focus of at least two companies. (7-Oct)
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IP and Process Solutions for Energy-efficient PMICs
Chalk Talk sponsored by ARM
Hierarchical Design Flows: Design Preservation & Team Design
Chalk Talk sponsored by Xilinx
Scalable Smart Debugging With ZeBu-Server
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Spartan-6 FPGAs in Video Designs
Chalk Talk sponsored by Xilinx
Teradici Success Story
White Paper sponsored by Synopsys
Reliable Reset Generation for TI DSP Processors
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FPGA Design Methods for Fast Turnaround
White Paper sponsored by Synopsys