A Horse of a Different Color

Advanced vs. Established Process Geometries

by Amelia Dalton

It's time to saddle up and ride into the semiconductor sunset! Whether you're hitchin' your wagon to a young whipper-snapper node, or lassoin' a long-in-the-tooth workhorse process, the time it takes to get your IC design up and out of the corral may depend more on the software you use to verify your design than on the silicon itself. In this week's Fish Fry, Mary Ann White (Synopsys) and I get down to the very heart of semiconductor design: process geometries. We have ourselves a good ol' time chatting about challenges of FinFET designs, the tricky bits of working with both advanced and established process nodes, and how the right tools can make all the difference when it comes to winning the big product-to-market rodeo.  Read More


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Editors' Blog

Planning PCB, Package, and Die Together

posted by Bryon Moyer

Cadence’s OrbitIO tries to tie together disparate tools and inefficient ways of planning pinouts. (31-Jul)

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EDA Editors' Blog Archive

forum

Middle Child Syndrome

Posted on 08/19/14 at 11:17 AM by kevin

kevin
Do you plan to do any design with 20nm? Do the benefits justify the incremental cost?

Life Under 20

Posted on 08/18/14 at 9:43 AM by bmoyer

bmoyer
We've seen new equipment for the 16/14 node... Are there other challenges at that node we haven't covered?

The Price of Ignorance

Posted on 08/17/14 at 1:19 PM by SteveNordquis4

SteveNordquis4
I'm pretty sure the $1000 power cord is either for supporting alt currency like 3 jingles and $140 for insured party-proof cord, 8% prix fixe vendor/installers, and audio equipment that has to be certified for surgery and/or commercial kitchen use (also s…

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