FPGA-Prototyping Simplified

Cadence Rolls New Protium Platform

by Kevin Morris

System on Chip (SoC) design today is an incredibly complicated collaborative endeavor. By applying the label “System” to the chips we design, we enter a realm of complex, interdisciplinary interactions that span realms like analog, digital, communications, semiconductor process, and - with increasing dominance - software. Since the first SoCs rolled out a mere decade or so ago, the composition of design teams has shifted notably, with the percentage of cubicles occupied by software developers increasing much more rapidly than those of any of the other engineering disciplines. In most SoC projects today, software development is the critical path, and the other components of the project are merely speed bumps in the software development spiral.  Read More


latest news

July 24, 2014

Cadence Introduces Three New OrCAD PCB Products Targeting Emerging Electronic Product Design Challenges

July 23, 2014

Mentor Graphics Launches New Xpedition Data Management Design Solution to Ensure Flow-Wide PCB Data Accuracy, Integrity, and Security for the Enterprise

ASSET and SoftIron collaborate on rapid debugging for 64-bit ARM-based enterprise servers using AppliedMicro's X-Gene technology

July 22, 2014

Real Intent Unveils Debug Enhancements in New Version of Ascent IIV for Static Verification of Digital Designs

Agilent Technologies’ PXIe Modular Vector Signal Test Solution Accelerates Smarter Micro’s Power Amplifier Development

July 21, 2014

Tektronix Showcases New and Enhanced Optical Test Solutions at ECOC 2014

July 17, 2014

Agilent Technologies Hosts 5G Test Summit at FuTURE MOBILE COMMUNICATION FORUM

Cadence Announces Protium Rapid Prototyping Platform and Expands System Development Suite Low-Power Verification

July 16, 2014

Mentor Graphics Launches Comprehensive Solution for Heterogeneous Multicore Embedded Software Development

July 15, 2014

Emulex Accelerates Verification Closure with Synopsys Verification IP for Ethernet

Cadence Announces Next-Generation Quantus QRC Extraction Solution, Delivering Best-in-Class Performance and Accuracy

Cadence Quantus QRC Extraction Solution Certified for TSMC 16nm FinFET

July 08, 2014

Synopsys Expands Verification IP Portfolio with Compliance Test Suites

Mentor Graphics Expands Automotive Portfolio, Acquires XS Embedded to Reduce Time to Start of Production (SOP)

Synopsys Cuts Area of DesignWare NVM IP for Automotive Grade 0 Applications by 75 Percent

EDA News Archive

Analog Breakthrough?

Pulsic Automates Analog Layout

by Bryon Moyer

Testing Big-Ass Transistors

Mentor’s Power Tester Accelerates Diagnosis

by Kevin Morris

Is the Classic Design Chain Broken?

Or Is It Just Another Step in Evolution?

by Dick Selwood

Challenged By FinFETs

Ansys’s Latest Redhawk Has to Work Harder

by Bryon Moyer

Baby Got DAC

The Design Automation Conference Returns to the City by the Bay

by Amelia Dalton

EDA Article Archive

 

Editors' Blog

Intelligent VIP

posted by Bryon Moyer

Arrow Devices focuses on building semantics into their VIP for a higher level of abstraction. (Yesterday)

Improved FPGA Tool Results

posted by Bryon Moyer

Plunify tries to get the best out of FPGA design tools (21-Jul)

Synopsys’s IP Initiative

posted by Bryon Moyer

Synopsys is taking a holistic view of SoC design using IP, including hardware and software elements. (17-Jun)

Mentor Unifies Verification

posted by Bryon Moyer

What used to be independent tools now serve a higher-level verification flow. (24-Apr)

New SEMulator 3D Announced

posted by Bryon Moyer

Coventor has released its next edition of their semiconductor process modeling tool. (16-Apr)

EDA Editors' Blog Archive

forum

Off to the Android Races

Posted on 07/24/14 at 9:23 AM by EEMBCpres

Hi. One quick comment pertaining to your sentence "Since the idea is to benchmark the platform, not the program, doubling up on optimized and non-optimized code makes sense."
EEMBC uses the terms peak and base, respectively, to refer to the CPU portion o…

Improved FPGA Tool Results

Posted on 07/23/14 at 8:38 PM by JohnSwan

JohnSwan
Fresh approach. They're exploring the constraint space in the cloud.

8-bit pixel sunglasses implore everyone around you to deal with it

Posted on 07/22/14 at 8:24 PM by SteveNordquis4

SteveNordquis4
It's Season 1 of CSI:Miami, surely; but the Poor Taste Conference cred. is surely the monopsony behind the production run.

EDA Forum Archive

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On Demand

Leading Up to PCI Express 4.0

Protium Rapid Prototyping Platform

Static Timing Analysis and Constraint Validation

Getting PCB Designs to Market Quickly with OrCAD PCB Design Tools at FTD Automation

Solving the ASIC Prototype Partition Problem with Synopsys ProtoCompiler

Announcing ProtoCompiler for Multi-FPGA Prototyping

Scripted Flows in Vivado Design Suite

Vivado Design Suite: Integrated Design Environment

Rigid-Flex and Embedded Components

Verify Design Performance with PADS Best-in-Class Simulation and Analysis

Maximize Your Power and Efficiency with PADS Interactive Placement and Routing

Cadence Low Power Solution - RTL to GDSII Low Power Design

Routing Interfaces Quickly & Efficiently on PCBs

Overcome the Challenges of Highly Constrained Designs

Cadence Tempus Timing Signoff Solution

Building a New Type of IP Factory

100G Ethernet Packet Parsing with Spacetime

It's the Software, Silly! - Success with FPGA-based Prototyping

EDA On Demand Archive


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