Go-Fast FPGA Design

Helpful Hot-Rodding Hints

by Kevin Morris

Most of us engineers are at least closet hot-rodders. It’s in our DNA. No matter how good a contraption is from the factory, we just can’t resist the temptation to tweak a few things in our own special way, and often that’s all about speed.

FPGA design, it turns out, is a big ‘ol blank canvas for hot-rodding. Even though we (fortunately) don’t have glossy convenience-store magazines adorned with scantily-clad models standing next to the latest tricked-out dev boards, FPGAs have all the tools we need to rev our creative motors in the never-ending quest for that extra little bit of personalized performance.

But, where do we start? Do FPGAs have a set of go-to hop-ups? Is there a “chopping and channeling” baseline for programmable logic design?

It turns out the answer is “yes.” And, just to get you started, here are five tips for turning up the boost on your next project:  Read More


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Editors' Blog

Faster Extraction from Cadence

posted by Bryon Moyer

Cadence has upgraded their parasitic extraction tools for the 16-nm node. (28-Aug)

Planning PCB, Package, and Die Together

posted by Bryon Moyer

Cadence’s OrbitIO tries to tie together disparate tools and inefficient ways of planning pinouts. (31-Jul)

Intelligent VIP

posted by Bryon Moyer

Arrow Devices focuses on building semantics into their VIP for a higher level of abstraction. (23-Jul)

Improved FPGA Tool Results

posted by Bryon Moyer

Plunify tries to get the best out of FPGA design tools (21-Jul)

Synopsys’s IP Initiative

posted by Bryon Moyer

Synopsys is taking a holistic view of SoC design using IP, including hardware and software elements. (17-Jun)

EDA Editors' Blog Archive

forum

Be a Better Programmer

Posted on 09/17/14 at 12:56 AM by juergenuk

juergenuk
Programmers put the bugs in. So they should get help where possible with tools and training to minimize. One way is to have a very rigid structure across the whole group.
On LinkedIN there was an interesting discussion, and some said: I want my programmi…

There’s a Processor in My FPGA!

Posted on 09/16/14 at 2:35 PM by SteveCasselman

Altera's OpenCL SDK allows software programmers to use the FPGA's fabric as easily as they use the processor cores. The same code that runs on an SoC also runs on the largest parts. Altera is also committed to having an SoC in each family so the Stratix 1…

Go-Fast FPGA Design

Posted on 09/16/14 at 1:23 PM by gabor@alacron.com

gabor@alacron.com
I'd add "Make room for heatsinks." Especially if you're packing the whole FPGA with logic and cranking up the clock, you will need help taking the heat from the chip. I've never regretted allowing extra room for a big heatsink, including board-level mou…

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