fish fry
Subscribe Now

Quantum Practicality and You: How Intel is Solving the Quantum Computing Interconnect Bottleneck

“A classical computation is like a solo voice—one line of pure tones succeeding each other. A quantum computation is like a symphony—many lines of tones interfering with one another.” – Seth Lloyd

In this week’s Fish Fry podcast, Stefano Pellerano (Intel Labs) joins me to discuss the interconnect challenges inherent in quantum computing, why frequency multiplexing is crucial to quantum scalability, and how Intel is bringing quantum computing out of the lab and into the real world. 

 

Click here to download this episode

Links for July 2, 2021

Intel and QuTech Demonstrate Advances in Solving Quantum Interconnect Bottlenecks

Intel Introduces ‘Horse Ridge’ to Enable Commercially Viable Quantum Computers

Fish Fry Special Edition: Makers Today! Karen Corbeill

 

Click here to check out the Fish Fry Archive.

Click here to subscribe to Fish Fry via Podbean

Click here to get the Fish Fry RSS Feed

Click here to subscribe to Fish Fry via Apple Podcasts.

Click here to subscribe to Fish Fry via Spotify

 

Fish Fry Executive Interviews

Anupam Bakshi, CEO – Agnisys

Dave Kleidermacher, CTO – Green Hills Software

Robert Blake, CEO – Achronix

Jack Harding, CEO – eSilicon

Michiel Ligthart, COO – Verific

Adnan Hamid, CEO – Breker Technologies

Simon Davidmann, CEO – Imperas

Jessica Gomez – Rogue Valley Microdevices

Shishpal Rawat, Chairman – Accellera Systems Initiative

Kevin Bromber, CEO – myDevices

Daniel Hansson, CEO – Verifyter

Mark Papermaster, CTO – AMD

David Fried, CTO – Coventor

Dr. Steven LeBoeuf, President – Valencell

David Dutton, CEO – Silvaco

Bob Niemiec, CEO – TwistThink

Allan Martinson, COO – Starship Technologies

Zhihong Liu, Chairman and CEO – ProPlus Solutions

Taher Madraswala, CEO and President – Open-Silicon

Kapil Shankar, CEO and Director – AnDAPT

Dan Fox, CTO – Local Motors

Kim Rowe, Founder and CEO — RoweBots

Lawrence Cooke, Founder and CEO — NovaSolix

Gregg Recupero, CTO — Performance-IP

Alan Grau, CEO — Icon Labs

Carl Alberty, Vice President – Cirrus Logic

Maximilian Odendahl, CEO — Silexica

Finbarr Moynihan, General Manager — MediaTek

Sanjay Pillay, CEO — Austemper

Louis Parks, CEO – SecureRF

Harold Blomquist, CEO – Helix Semiconductor

Dale Dougherty and Sherry Huss, Co-Founders – Maker Faire

David Su, CEO – Atomic Technologies

Leave a Reply

featured blogs
Oct 6, 2022
The days of 'throwing it over the wall' are over. Heterogeneous integration is ushering in a new era of silicon chip design with collaboration at its core'”one that lives or dies on seamless interaction between your analog and digital IC and package design teams. Heterogeneo...
Oct 4, 2022
We share 6 key advantages of cloud-based IC hardware design tools, including enhanced scalability, security, and access to AI-enabled EDA tools. The post 6 Reasons to Leverage IC Hardware Development in the Cloud appeared first on From Silicon To Software....
Sep 30, 2022
When I wrote my book 'Bebop to the Boolean Boogie,' it was certainly not my intention to lead 6-year-old boys astray....

featured video

PCIe Gen5 x16 Running on the Achronix VectorPath Accelerator Card

Sponsored by Achronix

In this demo, Achronix engineers show the VectorPath Accelerator Card successfully linking up to a PCIe Gen5 x16 host and write data to and read data from GDDR6 memory. The VectorPath accelerator card featuring the Speedster7t FPGA is one of the first FPGAs that can natively support this interface within its PCIe subsystem. Speedster7t FPGAs offer a revolutionary new architecture that Achronix developed to address the highest performance data acceleration challenges.

Click here for more information about the VectorPath Accelerator Card

featured paper

Algorithm Verification with FPGAs and ASICs

Sponsored by MathWorks

Developing new FPGA and ASIC designs involves implementing new algorithms, which presents challenges for verification for algorithm developers, hardware designers, and verification engineers. This eBook explores different aspects of hardware design verification and how you can use MATLAB and Simulink to reduce development effort and improve the quality of end products.

Click here to read more

featured chalk talk

Expanding SiliconMAX SLM to In-Field

Sponsored by Synopsys

In order to keep up with the rigorous pace of today’s electronic designs, we must have visibility into each step of our IC design lifecycle including debug, bring up and in-field operation. In this episode of Chalk Talk, Amelia Dalton chats with Steve Pateras from Synopsys about in-field infrastructure for silicon lifecycle management, the role that edge analytics play when it comes to in-field optimization, and how cloud analytics, runtime agents and SiliconMAX sensor analytics can provide you more information than ever before for the lifecycle of your IC design.

Click here for more information about SiliconMAX Silicon Lifecycle Management