EEJournal

fish fry
Subscribe Now
October 26, 2018

Operation: SIM

Security, Integration, and the IoC
by Amelia Dalton

“Captain’s log, Stardate 4211.4. Keeping our presence here secret… is an enormous tactical advantage.” – Captain Kirk

In this week’s episode of Fish Fry, we take a closer look at security in IoT devices with a little help from Rich Collins from Synopsys. Rich and I chat about the challenges of the SIM product lifecycle and why pre-verified hardware and software can make all the difference in your next design. Keeping with our IoT theme, we also check out why ultrasonic sensors are helping usher in a whole new era of cheesemaking.

 

 

Click here to download this episode 

Links for October 26, 2018

More information about DesignWare® tRoot™ Hardware Secure Module (HSM)

Synopsys and Truphone Enable Secure Over-the-Air Provisioning with Integrated SIM IP and Managed Services Solution

Only The Best Equipment can Produce the World’s Finest Cheeses: How the P53 Ultrasonic Sensor Improves Professional Cheese Making

Click here to check out the Fish Fry Archive.

Click here to subscribe to Fish Fry via Podbean

Click here to get the Fish Fry RSS Feed

Click here to subscribe to Fish Fry via iTunes.

Fish Fry Executive Interviews

Anupam Bakshi, CEO – Agnisys

Dave Kleidermacher, CTO – Green Hills Software

Robert Blake, CEO – Achronix

Jack Harding, CEO – eSilicon

Michiel Ligthart, COO – Verific

Adnan Hamid, CEO – Breker Technologies

Simon Davidmann, CEO – Imperas

Ted Miracco, CEO – SmartFlow Compliance Solutions

Jessica Gomez – Rogue Valley Microdevices

Shishpal Rawat, Chairman – Accellera Systems Initiative

Kevin Bromber, CEO – myDevices

Daniel Hansson, CEO – Verifyter

Mark Papermaster, CTO – AMD

David Fried, CTO – Coventor

Dr. Steven LeBoeuf, President – Valencell

David Dutton, CEO – Silvaco

Bob Niemiec, CEO – TwistThink

Allan Martinson, COO – Starship Technologies

Zhihong Liu, Chairman and CEO – ProPlus Solutions

Taher Madraswala, CEO and President – Open-Silicon

Kapil Shankar, CEO and Director – AnDAPT

Dan Fox, CTO – Local Motors

Lawrence Cooke, Founder and CEO — NovaSolix

Gregg Recupero, CTO — Performance-IP

Alan Grau, CEO — Icon Labs

Carl Alberty, Vice President – Cirrus Logic

Maximilian Odendahl, CEO — Silexica

Finbarr Moynihan, General Manager — MediaTek

Sanjay Pillay, CEO — Austemper

Louis Parks, CEO – SecureRF

Harold Blomquist, CEO – Helix Semiconductor

Dale Dougherty and Sherry Huss, Co-Founders – Maker Faire

Mike Wisart, CEO – efabless

Chris Giovanniello, SVP and Co-Founder – Menlo Micro

Jake Janovetz, President – Opal Kelly

Jerry Gipper, Executive Director – VITA

Ethan Plotkin, CEO – GDCA

Xin Song, CEO – Bottos

Chris Dries, CEO – UnitedSiC 

Bob Smith, Executive Director – ESD Alliance 

Rick O’Connor, Executive Director – RISC V Foundation

Naveed Sherwani, CEO and Yunsup Lee, CTO/Founder- SiFIve

Doug Letcher, CEO and President – Metrics Technologies

Jun Pei, CEO – Cepton Technologies

Nikos Zervas, CEO of CAST

Leave a Reply

featured blogs
Make a DATE with the Young People Programme
Dec 7, 2023
Building on the success of previous years, the 2024 edition of the DATE (Design, Automation and Test in Europe) conference will once again include the Young People Programme. The largest electronic design automation (EDA) conference in Europe, DATE will be held on 25-27 March...
More from Cadence...
The Importance of Memory Architecture for AI SoCs
Dec 7, 2023
Explore the different memory technologies at the heart of AI SoC memory architecture and learn about the advantages of SRAM, ReRAM, MRAM, and beyond.The post The Importance of Memory Architecture for AI SoCs appeared first on Chip Design....
More from Synopsys...
A Haunting World Underwater
Nov 6, 2023
Suffice it to say that everyone and everything in these images was shot in-camera underwater, and that the results truly are haunting....
More from Max's Cool Beans...

featured video

Dramatically Improve PPA and Productivity with Generative AI

Sponsored by Cadence Design Systems

Discover how you can quickly optimize flows for many blocks concurrently and use that knowledge for your next design. The Cadence Cerebrus Intelligent Chip Explorer is a revolutionary, AI-driven, automated approach to chip design flow optimization. Block engineers specify the design goals, and generative AI features within Cadence Cerebrus Explorer will intelligently optimize the design to meet the power, performance, and area (PPA) goals in a completely automated way.

Click here for more information

featured paper

Power and Performance Analysis of FIR Filters and FFTs on Intel Agilex® 7 FPGAs

Sponsored by Intel

Learn about the Future of Intel Programmable Solutions Group at intel.com/leap. The power and performance efficiency of digital signal processing (DSP) workloads play a significant role in the evolution of modern-day technology. Compare benchmarks of finite impulse response (FIR) filters and fast Fourier transform (FFT) designs on Intel Agilex® 7 FPGAs to publicly available results from AMD’s Versal* FPGAs and artificial intelligence engines.

Read more

featured chalk talk

Telematics, Connectivity & Infotainment Integration Made Easy
Sponsored by Mouser Electronics and NXP Semiconductors and u-blox
Today’s automotive designs must contend with a variety of challenges including scalability, security, software integration and the increased use of different radio technologies. In this episode of Chalk Talk, Fredrik Lonegard from u-blox, Patrick Stilwell from NXP and Amelia Dalton explore how the use of modules can help address a variety of automotive design challenges and the benefits that ublox’s JODY-W3 host-based modules can bring to your next automotive application.
Click here for more information  about u-blox JODY-W3 Host-Based Automotive Modules
Apr 4, 2023
29,565 views