Sensing a New Generation

How Wearables Will Revolutionize Prenatal Medicine

by Amelia Dalton

In this week’s Fish Fry we explore a whole new world of wearable technologies with Julian Penders from Bloom Technologies. Julian (co-author of “Wearable Technologies for Healthier Pregnancies”) and I talk about how wearable technologies can help monitor lifestyle behaviors. We’ll be looking at the future of wearable technologies targeted for pregnancy, and discussing how these technologies pose additional challenges. Also this week, I check out Cadence’s new Innovus tool suite and reveal how it could make routing your million gate IC design just a little bit easier.  Read More

Industry News

July 03, 2015

Saelig Introduces Versatile Dual Channel 13.6GHz Microwave Signal Generator

European collaboration accelerates silicon photonics prototyping services

Canal+ Group Unveils New Hybrid OTT / HD Broadcast Set-Top Box Powered by Frog by Wyplay Middleware and STMicroelectronics

Cliff’s patented Dual DC Socket proves 2 into 1 will go

July 02, 2015

Mouser Unveils Enhanced Internet of Things Applications Site

9-45V & 16-80V input range, 150W DC-DC converters now in a 1/4 brick package

TI introduces the first brushed DC gate driver with adjustable current drive capability for scalable designs

ADLINK Extends 3U VPX Product Portfolio to Include Rugged, High Performance GPGPU Blade

Mouser and Imahara Launch New Home and Factory Automation Series to Connect Engineers to the Latest Innovations in Technology

Xilinx Tapes-Out Industry’s First All Programmable Multi-Processor SoC Using TSMC’s 16nm FF+ for Embedded Vision, ADAS, I-IoT, and 5G Systems

Nallatech 510T FPGA Accelerator Disrupts the Datacenter

July 01, 2015

Excelsys Technologies’ New powerMod Plug-in DC Modules are Optimised for Reactive Loads

GreenPeak’s new multi-channel chipset simultaneously supports ZigBee and Thread networks

Avalue introduces new BSW series Embedded Boards – EBM-BSW, EQM-BSW and ESM-BSW, based on Intel® Pentium®/Celeron® processor N3000 family

Super-Fast Switching Diodes from Diodes Incorporated Deliver Ultra-Low Leakage

June 30, 2015

Wind River Simics Advances Agile Practices for IoT Development

Zuken Offers Improved Productivity and Enhanced Collaboration with Latest E³.series Release

XP Power leads the industry with 95% efficient 225 Watt AC-DC supply in a 2” x 4” package

Sensory Releases Embedded Speaker Verification SDK - Enables Devices to Switch User Profiles Based on Who's Talking

Quicker System Boot Time & Power Analysis with 13A to 100A Digital Interface µModule Regulator

TE Connectivity’s Micro Circular Connectors Now Available Globally

TI introduces the first brushed DC gate driver with adjustable current drive capability for scalable designs

Renesas Electronics Delivers Industry-Leading Power Efficiency and Digital Filtering Capabilities for Industrial Sensor and Healthcare Design with RX231 Microcontrollers

June 29, 2015

Microchip Announces Projected-Capacitive Touch Screen Controller With Noise-Robust, Advanced Multi-Touch and Gesture Performance

Evaluation Kit demonstrates innovative Energy Harvesting Switch Technology from CHERRY

TE Connectivity and Andretti Technologies Team up to Advance Technology in Autosports and Electric Vehicles

Artila releases machine-to-machine (M2M) sensors and actuators solution

Universal Temperature Sensor IC with EEPROM Targets Modular & Custom Sensor Systems

News Archive

Apple Hints at CPU and OS Independence

New Bitcode Format Could Be the First Step Toward CPU-Neutral Platforms

by Jim Turley

Selling Your Brain

Patent Law is a Slippery Slope for Engineers

by Kevin Morris

IoT Security

Hints of Solutions to Come

by Bryon Moyer

Treasure of the Semiconductor Madre

Seeking EDA Gold (and Answers) with Xerxes Wania

by Amelia Dalton

Articles Archive


Featured Video

editors' blog

Detailed RTL Power Analysis

posted by Bryon Moyer

Mentor has consorted (carefully) with a competitor to provide a path to faster RTL power analysis. (18-Jun)

Apple Hints at CPU Change

posted by Jim Turley

Apple's new "Bitcode" software-distribution mechanism lays the groundwork for a switch in CPU architecture, operating system, or both. (18-Jun)

Ayla’s Mobile App Platform

posted by Bryon Moyer

Ayla Networks wants to make it easier for you to build a phone app that will talk to your IoT widget. (16-Jun)

New Toy in the Sandpit

posted by Dick Selwood

EDA Playground has a new toy (12-Jun)

The Essence of Big Data

posted by Bryon Moyer

What’s the big deal with Big Data? (11-Jun)

Editors' Blog Archive



IoT Security

Posted on 06/29/15 at 11:43 AM by TotallyLost

As stated in the article, the more complex the IoT solution is, the more points there will be for exploits.

The real problem is the complete lack of old school KISS -- Keep It Simple Stupid!!!

There is significant security in a $100 bill, targeted s…

After Intel and Altera

Posted on 06/27/15 at 9:46 AM by gobeavs

What will happen next is that Xilinx will get bought too. That seems to be the pattern in the semiconductor industry. If Broadcom and Altera can get bought so can Xilinx. Semiconductor industry is consolidating rapidly.

Maximizing Flash Lifetimes

Posted on 06/24/15 at 4:06 PM by Lord Loh.

Lord Loh.

This article appeared in 2012. Macronix was annealing flash to extend it's life.

Does anyone know whether it has been commercialised yet? or Licensed out?

After Intel and Altera

Posted on 06/24/15 at 12:29 AM by beercandyman

Intel will use it's sales force to get FPGAs into places that Altera never sold into before. While Intel loves margins they can take lower margins with strategic accounts that Xilinx won't be able to match. Also Intel makes boards. Altera and Xilinx only …


Posted on 06/23/15 at 11:56 PM by bmoyer

I'll see if I can get a more detailed response out of Imec. I suspect the qualification is with "just like Al" - that it can be etched just like Al can be etched, but they're doing something different that they're not disclosing.

After Intel and Altera

Posted on 06/23/15 at 2:49 PM by qursan

Intel is a poor player in the Architecture field. It certainly produced one of the most successful CPU architectures in the industry (besides the ARM). However, it always relied on its circuit design and semiconductor strength to improve performance. A si…


Posted on 06/23/15 at 12:30 PM by MistyMcGarr

So thinner copper is able to be etched like aluminum but the thicker copper of yesterday was not? What gas are you using to etch the copper today? According to you can etch AL but not CU?

After Intel and Altera

Posted on 06/23/15 at 12:14 PM by TotallyLost

There isn't a "one size fits all solution", and this is where it's going to get really fun.

Over the last decade accelerated math FPGA's ended up with a large number of DSP IP blocks optimized for certain FFT and matrix operations.

Network and perip…

After Intel and Altera

Posted on 06/23/15 at 10:33 AM by fredriknyman

Intel does a substantial amount of networking stuff too. NICs, switch silicon and what have you. If they were to start putting FPGA fabric there, it would make be a game changer for SDN.

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Featured Chalk Talk

On Demand Archive

chalk talks

PADS VX: Redefining Productivity

When it comes to PCB Design, the giant companies don't get ALL the cool toys. Desktop design tools are now getting impressive capabilities that rival their enterprise-scale big brothers. In this episode of Chalk Talk, Amelia Dalton talks with Jim Martens of Mentor Graphics about the new PADS VX and the impressive capabilities it brings to desktop electronic design.

USB Type-C Solutions

USB Type-C is coming, but how will you add it to your design? In this episode of Chalk Talk, Amelia Dalton chats with Gordon Hands of Lattice Semiconductor about a great new flexible solution for USB Type-C. Your job may be easier than you think.

Vivado IP Integrator

Even the best "plug and play" IP blocks are far from fool-proof. One of the most challenging aspects of IP-based design can be getting the blocks stitched together properly, making sure you have the right version of all the IP blocks, and confirming the configuration of your whole design. In this episode of Chalk Talk, Amelia Dalton chats with Tim Vanevenhoven about the powerful correct-by-construction automation built into the IP Integrator in Vivado Design Suite from Xilinx. IP Integrator seriously raises the bar on automation of IP-based design.

Scripted Flows in Vivado Design Suite

When you're using a new tool for the first time, a good GUI is great to have, but once you're up and running and automating a complex design process, scripted flows offer a much more powerful means of controlling your tools. In this episode of Chalk Talk, Amelia Dalton and Ron Plyler of Xilinx explore scripted flows in the Vivado design suite.

Physically Aware Synthesis Techniques to Lower Power, Improve Timing, Congestion & Correlation

Synthesis is the single most important step in creating a high-quality implementation of our design. But, we can't expect our synthesis tool to produce the best results without considering the very important effects of routing delay introduced by placement and routing. In this episode of Chalk Talk, Amelia Dalton talks with David Stratman of Cadence about how to apply physically-aware synthesis techniques to improve the overall quality of your design.

Abstract and Conquer: A New Alternative to Hierarchical Timing Analysis

Sign-off timing analysis for today’s complex SoC designs can be daunting. Rather than just throwing more computer power at the problem, you need to adopt a hierarchical approach and take advantage of higher levels of abstraction. In this episode of Chalk Talk, Amelia Dalton talks with Ruben Molina of Cadence Design Systems about a new, faster approach to sign-off timing analysis.

Delivering Higher FPGA Utilization & Performance: UltraScale Architecture

Ever notice how hard it can be to get the full utilization that an FPGA datasheet promises? Xilinx is aiming to change all that. In this episode of Chalk Talk, Amelia Dalton talks with Darren Zacher of Xilinx about the new Ultrascale FPGA family, and how the architecture has been optimized for maximum utilization.

Chalk Talk Archive

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