Programmable Pile of Parts

FPGAs were conceived as “do anything” chips – Jacks of all Trades. Sure, they were crazy expensive for the number of effective gates they offered, they were a lot slower than custom logic doing the same task, and they drank copious quantities of coulombs getting the job done, but they could be programmed to do exactly your bidding. In a lot of designs, that made the FPGA the no-longer-missing link – … Read More → "Programmable Pile of Parts"

Zap! Zap! Zap! GlobalFoundries’ UHV 180nm Process Hits 700V

Thunder is good, thunder is impressive; but it is lightning that does the work. – Mark Twain

With all the media hype and heavy emphasis on the leading-edge semiconductor process technologies that will soon reach single-digit nanometer numbers, working-class process technologies often get no respect. That’s why I was so pleased to learn that GlobalFoundries Read More → "Zap! Zap! Zap! GlobalFoundries’ UHV 180nm Process Hits 700V"

Amazon and Google in the RTOS World

“One ring to bring them all and in the darkness bind them.” – J.R.R. Tolkien, The Lord of the Rings

Monkey see, monkey do. Google acquired Android years ago and turned it into a hugely successful tool for embedded programmers. Now, Amazon has taken over FreeRTOS. Will it become the next Android, a de facto standard for real-time software that … Read More → "Amazon and Google in the RTOS World"

An MRAM Cell that Competes with SRAM?

Anything you do can be done efficiently or not. Whether it’s driving (mpg?), playing sportsball (results/energy spent?), or walking the dog (who pulls whom?), you can be efficient or not. Obviously, higher efficiency is better – assuming you care (sometimes spending energy worrying about efficiency can be inefficient). So… what if you could identify an improvement for an activity you care about that, by itself, … Read More → "An MRAM Cell that Competes with SRAM?"

There’s No Business like EDA Business

In this week’s podcast, we welcome Bob Smith from the Electronic System Design (ESD) Alliance to Fish Fry. Bob and I are chat about why the ESD Alliance and SEMI are joining forces, the ESD Alliance’s plans for DAC this year, and we even fit in a little discussion about wine. Also this week, we check out the new artificial intelligence and machine learning program at this … Read More → "There’s No Business like EDA Business"

June 22, 2018
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June 15, 2018
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June 13, 2018
Posted on Jun 19 at 10:03am by Dick Selwood
FreeRTOS is only a part of a tool offering from Amazon. As I wrote in December: "AWS has a huge number of offerings for the IoT, including AI at the edge, and analytics, machine learning, etc. in the cloud. Clearly AWS want to make it easy for their users to ...
Posted on Jun 18 at 9:43am by Bryon Moyer
What do you think of STT's approach to MRAM that could replace SRAM?
Posted on Jun 15 at 9:03am by TotallyLost
First, from the NTSB quote above, NO "alerts were made more than 15 minutes prior to the crash." for the driver to place his hands on the wheel, so the driver was keeping the systems satisfied. This is confirmed by the NTSB quote above: During the 60 seconds prior to the crash, ...
Posted on Jun 12 at 1:31pm by Headworx
Unfortunately the tests presented do not reflect real life use cases. Essentially it was a single packet traversing a network. No concurrency at all (no multiple message originators). The devil is in the details...
Posted on Jun 12 at 7:51am by Dick Selwood
So mesh networking was invented in 1956 by Dodie Smith, the English author of the book One Hundred and One Dalmatians? Packet switching invented at the National Physical Laboratory by the Welshman, Donald Davies in 1965. World Wide Web by Sir Tim Berners-Lee in 1989. Hoorah for Britain!
Posted on Jun 11 at 12:03pm by SteveNordquis4
I came for the segmented cache bus concurrency upgrade and the smoked tea, and I'm all out of directives posing as arbitrary operators, maybe? Is there not an inset image of the likely IP changes over the variant universe and a fab roadmap detail just yet; or is ...
Posted on Jun 11 at 10:44am by SteveNordquis4
Good: The landlord used to work in Oil & Gas Field Tech so they won't be flipping them like crazy. Bad: They've been collecting a lot of reusable takeaway and LP lines... Spec: Cavitation isn't as bad as they say once you get used to it.
Posted on Jun 11 at 10:12am by Bryon Moyer
What do you think of the wireless mesh comparison from Silicon Labs?
Posted on Jun 11 at 5:01am by Christoforos
If we want FPGAs to make it to the data center and cloud computing world, we need to decouple the FPGA IP core developers from the cloud developers that will use these IPs through an easy to use interface and a common marketplace (e.g. aws marcketplace.) We are working ...
Posted on Jun 8 at 10:46am by mattb
Hi Steve - great comparison! MiniZed also has development flows that abstract the complexity of SoC minutia, such as Xilinx SDSoC as well as Simulink from MathWorks.
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featured blogs
Jun 22, 2018
Last time I worked for Cadence in the early 2000s, Adriaan Ligtenberg ran methodology services and, in particular, something we called Virtual CAD. The idea of Virtual CAD was to allow companies to outsource their CAD group to Cadence. In effect, we would be the CAD group for...
Jun 21, 2018
Doing business today isn’t quite like it was back in the 80’s. Sparkling teeth and x-ray vision shouldn’t be a side effect of a customer using your product. This, of course, is said in jest, but no longer do we sell only a product; but a product and physical...
Jun 7, 2018
If integrating an embedded FPGA (eFPGA) into your ASIC or SoC design strikes you as odd, it shouldn'€™t. ICs have been absorbing almost every component on a circuit board for decades, starting with transistors, resistors, and capacitors '€” then progressing to gates, ALUs...
May 24, 2018
Amazon has apparently had an Echo hiccup of the sort that would give customers bad dreams. It sent a random conversation to a random contact. A couple had installed numerous Alexa-enabled devices in the home. At some point, they had a conversation '€“ as couples are wont to...
Apr 27, 2018
A sound constraint management design process helps to foster a correct-by-design approach, reduces time-to-market, and ultimately optimizes the design process'€”eliminating the undefined, error-prone methods of the past. Here are five questions to ask......
chalk talks
Maxim’s DARWIN Low Power Microcontrollers   MCUs continue to evolve based on increasing demands from designers. We expect our microcontrollers to do more than ever – better security, more performance, lower power consumption – and we want it all for less money, of course. In this episode of Chalk Talk, Amelia Dalton chats with Kris Ardis from Maxim Integrated … Read More → "Maxim’s DARWIN Low Power Microcontrollers"
PolySwitch PPTC Devices and Applications   Sometimes you’d like to just press reset after an overcurrent event. For those kinds of designs, a PPTC device is exactly what you need. In this episode of Chalk Talk, Amelia Dalton talks to Eric Lineman from Littelfuse about resettable overcurrent protection with PolySwitch PPTC, and how it can help your next design. … Read More → "PolySwitch PPTC Devices and Applications"
Bringing Arduino Into the Professional Environment  Arduino can be an excellent platform for professional/commercial application development and deployment. While most engineers associate Arduino with hobby and maker use, Microchip Technology has developed tools and platforms that bring the convenience and ease of Arduino into the professional realm. In this episode of Chalk Talk, Amelia Dalton chats with Bob Martin from … Read More → "Bringing Arduino Into the Professional Environment"
Debug and Verify FPGA Algorithms with MATLAB and Simulink   Today’s FPGA designs require industrial-strength functional verification. The ad-hoc methods that worked with older, smaller FPGAs just don’t cut it anymore. In this episode of Chalk Talk, Amelia Dalton chats with Eric Cigan of MathWorks about ASIC-strength functional verification with model-based design. Click here for more information about how to verify VHDL and … Read More → "Debug and Verify FPGA Algorithms with MATLAB and Simulink"
Intelligent Power Modules  Intelligent power modules can speed up your project, improve your power consumption, and bring a host of other benefits to your design. In this episode of Chalk Talk, Amelia Dalton chats with David Divins from Infineon about using Infineon’s intelligent power modules in your next project. Click here for more information about Infineon Technologies … Read More → "Intelligent Power Modules"
Simulation-Based Tuning of Power Electronics Controllers   Power electronics are becoming more complex these days, and simulating your digital power controller gives significant advantages. In this episode of Chalk Talk, Amelia Dalton chats with Arkadiy Turevskiy of MathWorks about how to tune digital power electronics controllers with simulation. Click here for more information about Simulation-Based Tuning of Power Electronics Controllers.