Safety (and Security) First

Embedded Software, TÜV Certification, and 64 bits

by Amelia Dalton

In this week’s Fish Fry, we’re taking on safety, security, and the embedded design software in between. Michael May (Express Logic) and I start things off with an in-depth discussion about the ongoing design-in battle between 32 and 64 bit processors and where ThreadX RTOS fits into the embedded ecosystem. Keeping with this week’s embedded software theme, I also chat with Jim McElroy (LDRA) about what we need to do when our designs must adhere to a security-critical standard, why TÜV Certification is so important, and what it's like to captain a whale watching boat.  Read More


Industry News

February 05, 2016

Ultra compact global 3G/2G cellular module ideal for tracking and IoT applications

Keysight Technologies Announces ADS 2016, its Latest Advanced Design System Software Release

Mirabilis Design announces the industry-first Electronic System-Level Memory Model library to accelerate the trade-off memory architectures

HRL Laboratories’ Breakthrough May Pave the Way for Gallium Nitride to Supplant Silicon in Integrated Circuits

Keysight Technologies Introduces Industry’s First Hybrid Memory Cube Compliance Test Software

February 04, 2016

Xilinx Announces Data Center Ecosystem Investment Program to Broaden Cloud Computing and NFV Acceleration Solutions

Imec and Holst Centre Present Wi-Fi HaLow Low-Power Fully Digital Polar Transmitter for IoT Applications

36V, 800mA Robust Linear Regulator Has Extended SOA Plus Current & Temperature Monitor Outputs

February 03, 2016

Synopsys' 10 Gbps USB 3.1 IP First to Pass USB-IF Certification

Imec and Vrije Universiteit Brussel Present Small, Low-Cost and Low-Power Chip for multi-gigabit 60GHz Communication

Dialog Semiconductor Expands Power Management Market with Industry's first PMICs for Smart TVs and Set-top Boxes

Optimal+ Announces Big Data Analytics Support for NI Semiconductor Test System

Xilinx Transceiver Breakthrough Brings Greater Cost Efficiency to Data Center Interconnects

Renesas Electronics Develops 90 nm One-Transistor MONOS Flash Memory Technology to Accelerate Intelligence in Automotive Control Systems

First Compliance Verification Process for Ethernet ECUs

Synopsys Redefines Circuit Simulation with Native Environment

February 02, 2016

TI drives high-voltage batteries with industry’s first 100-V high-side FET driver

Renesas Electronics Develops Camera Video Processing Circuit Block with Low Latency, High Performance, and Low Power Consumption for Automotive Computing SoC for the Autonomous-Driving Era

New eXtremeDB 7.0 DBMS Adds Powerful Features to Cement its Key Role on the Internet of Things

New Cadence Modus Test Solution Delivers Up to 3X Reduction in SoC Test Time

Renesas Electronics Develops Hardware Fault Detection and Prediction Technologies to Support Functional Safety Standards for Automotive Computing Systems for the Autonomous-Driving Era

February 01, 2016

Cadence Announces Complete Digital and Signoff Reference Flow for Imagination Technologies' PowerVR Series7 GPUs

Keysight Technologies Demonstrates PCIe® 4.0 Test Solutions at DesignCon

u-blox to demonstrate NB-IoT technology at Mobile World Congress

Avnet Introduces Agate IoT Solution in the Americas

News Archive

Magnets Help the Harvest

Two Totally Different Techniques

by Bryon Moyer

Xilinx 1, Intel 0

Big X Scores First in the New Rivalry

by Kevin Morris

When Things Get Weird

When is the Right Time to Ditch the Standard and Go Your Own Way?

by Jim Turley

How It’s Built: Micron/Intel 3D NAND

Micron Opens the Veil a Little

by Bryon Moyer

Articles Archive

 

Featured Video

Featured Chalk Talk

 

forum

Xilinx 1, Intel 0

Posted on 02/06/16 at 1:06 PM by beercandyman

I'll just point out that TSMC 16nm is really just 20nm with a finfet. I'll also point out that the latest part from Xilinx is just a little bigger than their last part. Altera did a big change in the architecture of the Stratix 10. For example single prec…

Magnets Help the Harvest

Posted on 02/04/16 at 10:07 PM by TotallyLost

TotallyLost
In the first case with the fan and magnets, anything that increases loading of the fan, will incur losses in the fan motor, in addition to what is coupled off.

Now assuming you really need to move the air for cooling something, then the proper engineer…

Magnets Help the Harvest

Posted on 02/04/16 at 11:24 AM by bmoyer

bmoyer
What do you think of these magnetic energy harvesting ideas? Attractive? Repulsive?

FPGA Synthesis Showdown

Posted on 02/03/16 at 1:55 PM by TotallyLost

TotallyLost
@gobeavs ... I don't think your anonymously attacking Kevin directly and personally in this or any other industry forum has cause, and is certainly way below the degree of professionalism other readers in this forum expect and deserve.

What ever person…

How It’s Built: Micron/Intel 3D NAND

Posted on 02/01/16 at 10:12 AM by bmoyer

bmoyer
What do you think of Micron and Intel's approach to 3D NAND?

Towards Silicon Convergence

Posted on 01/29/16 at 2:36 PM by mrburich

Intel's acquisition of Altera answers the "who is the integrator" question.

Getting Creative with Standards

Posted on 01/27/16 at 12:41 PM by samlefler

Good standards create markets and provide capital that drives innovation: BLE, USB and RS232 as an example.

This year CES featured large number of innovative products based on Bluetooth Smart standard.

For me, standards are my work and innovation is…

Forum Archive

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Featured Blogs

Xilinx, Inc.

February 6, 2016
  The latest FPGA-compatible TICO encoder and decoder compression IP cores from intoPIX support 4K/UHD video—they’re also 8K-capable—with a 4:4:4 color space (8-, 10-, or 12-bit color depth) using a variable, visually lossless data-compression ratio …
 

More from Xilinx, Inc....

Cadence

February 5, 2016
We are all familiar with it. Every year, designs get faster, smaller, and more complicated. Whether your newest package has a towering stack of memory dies placed into a cavity or a few massive flip-chips with critical bus lanes between them, it never fai…
 

More from Cadence...

Mentor Graphics Corp.

February 2, 2016
Multicore designs in embedded systems are now becoming mainstream as the cost-effective way to implement the complex functionality required in modern devices. There are essentially two multicore system architectures – AMP and SMP. SMP [Symmetrical M…
 

More from Mentor Graphics Corp....

EE Journal Editors' Blog

February 1, 2016
I ran across a series that deals with some of the less-touted possible outcomes of the technology work we do. It’s actually a few years old, but, while edgy and possibly challenging for some to watch, I also found it thought-provoking.....
 

More from EE Journal Editors' Blog...

Altera

January 18, 2016
As one security expert has said, system security is not a thing, it is a process. In our increasingly connected—and increasingly hostile—environment, security has become a continuous case of new attacks leading to new countermeasures, followed by more inn…
 

More from Altera...

Featured Blogs Archive

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Featured Paper

chalk talks

Cadence Tensilica Vision P5

Intelligent vision systems represent some of today's biggest embedded design challenges. The enormous processing power required combined with small energy budgets rules out most conventional applications processors. In this episode of Chalk Talk, Amelia Dalton chats with Dennis Crespo from Cadence Design Systems about the new Tensilica Vision P5 processors - designed specifically to meet the needs of embedded vision applications.

Introducing Palladium Z1 Enterprise Emulation Platform

Emulation is critical in the development of just about every complex IC these days, but most emulation systems are burdened with proprietary standards and form factors that don't scale well. In this episode of Chalk Talk, Amelia Dalton talks with Frank Schirrmeister of Cadence Design Systems about the new Palladium Z1 datacenter-class emulation system, which was designed with the capacity and scalability required for today's most challenging designs.

Analog to Digital Conversion

High speed analog signals pose special challenges for analog-to-digital conversion (ADC). Applications like software-defined radio, radar, instrumentation, and high-speed wireless require ADC that is high-performance, high-accuracy, and low power. In this episode of Chalk Talk, Amelia Dalton chats with Trent Butcher of Microchip Technology about solving the issues of high-speed ADC.

M8/M12 Connector System

For industrial-grade applications, consumer-style connectors just don't cut it. You'd never use RJ45 where you really care about ruggedness or reliability. In this episode of Chalk Talk, Amelia Dalton chats with Tom Wess of TE Connectivity about M8 and M12 high-reliability connectivity solutions that will keep your system operating smoothly under harsh conditions.

Altera 2.5Gb Ethernet IP

Even though the newest, fastest standards get all the press, most of the work in the world is being done by standards like 2.5G Ethernet. In this episode of Chalk Talk, Amelia Dalton chats with Juwayriyah Hussain of Altera about Altera's IP for 2.5G Ethernet. It'll have you up and running with Ethernet on your next design in no time.

Meet ARTY: the $99 FPGA Development Kit from Xilinx

Have you been wanting to try FPGA design? Were FPGA development boards and tools always too expensive and difficult to use? In this episode of Chalk Talk, Amelia Dalton chats with Darren Zacher and Jim Burnham of Xilinx about ARTY, a new, easy-to-use $99 FPGA-based embedded development kit from Xilinx.

Chalk Talk Archive


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