Where’s the CNN Synthesis?

The electronic design automation (EDA’s) mission has always been primarily to facilitate the design and verification of electronic circuits. EDA began, of course, with companies like Mentor, Daisy, and Valid providing specialized software for capturing and editing schematic drawings. These tools took the native human-readable language of the designer: schematics, and created the fundamental machine-readable structure of EDA: the netlist.

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The New, New Intel Unleashes a Technology Barrage

“3D XPoint is nothing short of a miracle.” – Alber Ilkbahar

Intel just celebrated the start of its 50th year. For those who were not following closely in 1968, Robert Noyce and Gordon Moore founded Intel Corporation on July 18 of that year. That’s a year after the Summer of Love and … Read More → "The New, New Intel Unleashes a Technology Barrage"

BARR-C Aims to Make Us Better Programmers

“I’d spell ‘creat’ with an e.” – Ken Thompson, when asked what he’d change about Unix.

Look up “panacea” and you’ll find a bunch of C programming tools. Everyone and his dog has ideas about how to create better, more reliable C code. Use an ISO-certified compiler. Follow MISRA C guidelines. Write the comments first. Agile Programming. Energy crystals. The … Read More → "BARR-C Aims to Make Us Better Programmers"

A More Reliable MRAM Mechanism

The search continues for the perfect memory cell that will replace SRAM, DRAM, and flash memory cells with better performance, power, and reliability characteristics than any of those three. While we’ve seen a number of contenders, there isn’t really any cell that is optimal for all three. Typically, cells will target either SRAM (and maybe DRAM) for in-operation memory, or flash for long-term storage.Read More → "A More Reliable MRAM Mechanism"

Programmability’s Promise

Need programmability? Step right up my friends. In this week’s Fish Fry, we are investigating some of the newest and coolest applications using programmable technology today. Ted Marena (Microsemi) demonstrates how we can use PolarFire FPGAs in a machine-learning application and how this PolarFire FPGA-based board can also facilitate Linux and RISC-V development. Sunder Parameswaran (Falcon Computing) also joins us to discuss some really cool applications for FPGA … Read More → "Programmability’s Promise"

Re-interpreting Moore’s Law

For two or three decades, there has been raging debate about the longevity and relevance of Moore’s Law. Is it dead? Has it changed? Is it slowly fizzling out? Was it a law or just a projection? Is it really about transistor density only, or something more conceptual? Did Moore really say “doubles every two years” or was it more like 18 months? Was Moore’s … Read More → "Re-interpreting Moore’s Law"

August 16, 2018
August 15, 2018
August 14, 2018
August 13, 2018
August 9, 2018
August 8, 2018
August 7, 2018
August 6, 2018
August 3, 2018
August 2, 2018
Posted on Aug 13 at 8:31am by Bryon Moyer
What do you think the prospects are for SOT-MRAM?
Posted on Aug 10 at 4:07am by leftygoldblatt
https://arxiv.org/ftp/arxiv/papers/1801/1801.05215.pdf "However, the flip side of the death of Moore’s Law will be a significant decrease in cost of chip fabrication, since manufacturing industries will not need to replace their equipment so often, and their investments in process technology will be drastically reduced. ...
Posted on Aug 8 at 10:23am by leem12000
Kevin, I am not sure how you became the author of this piece as I am the author of this when I was at Mentor Graphics. Can you please update and provide credit to the proper author, me? Thx, Mike Lee
Posted on Aug 6 at 8:57am by Bryon Moyer
What do you think of Irdeto's approaches to securing software?
Posted on Aug 1 at 8:46am by Kev
X-pessimism is an artificial problem caused by the bad/compact signal used by the original Verilog. Nowadays you can use nettypes in SystemVerilog and split out the components of the signal so that the uncertainty (X) is just tags saying you forgot to do things (like reset, power,...) and the ...
Posted on Jul 31 at 8:49am by Bryon Moyer
What do you think of Real Intent's gate-level X-pessimism and CDC solutions?
Posted on Jul 30 at 2:18pm by Karl Stevens
Well, he never got around to anything about RISC-V being the answer -- only his pipe dream of world domination. This quote "DSAs perform certain specific tasks better because they are not general purpose. Instead, they solve classes of problems that offer more opportunities to exploit parallelism. DSAs also use ...
Posted on Jul 25 at 2:35pm by cpetras
Posted on Jul 24 at 9:27pm by TotallyLost
I made the K.I.S.S comment out of frustration. Engineering is about setting clear goals and specifications that are verifiable, and designing to that. It's NOT about picking some technology out of the hat, and applying it to a pet solution, and calling it good without any serious ...
Posted on Jul 23 at 3:55pm by TotallyLost
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featured blogs
Aug 16, 2018
All of the little details were squared up when the check-plots came out for "final" review. Those same preliminary files were shared with the fab and assembly units and, of course, the vendors have c...
Aug 16, 2018
Usually I don't go to the last day of SEMICON West since not much happens that day. But they have got smart, and two of the most interesting sessions took place in TechXPOT (I think you pronounce that Techspot) on Thursday. In the afternoon was Scaling Every Which Way ab...
Aug 15, 2018
VITA 57.4 FMC+ Standard As an ANSI/VITA member, Samtec supports the release of the new ANSI/VITA 57.4-2018 FPGA Mezzanine Card Plus Standard. VITA 57.4, also referred to as FMC+, expands upon the I/O capabilities defined in ANSI/VITA 57.1 FMC by adding two new connectors that...
Aug 14, 2018
I worked at HP in Ft. Collins, Colorado back in the 1970s. It was a heady experience. We were designing and building early, pre-PC desktop computers and we owned the market back then. The division I worked for eventually migrated to 32-bit workstations, chased from the deskto...
Jul 30, 2018
As discussed in part 1 of this blog post, each instance of an Achronix Speedcore eFPGA in your ASIC or SoC design must be configured after the system powers up because Speedcore eFPGAs employ nonvolatile SRAM technology to store its configuration bits. The time required to pr...
chalk talks
HAPS-80 Desktop Prototyping Solution   High-performance FPGA-based prototyping has moved to the desktop. Validation of hardware and software interoperability can now be much more convenient and productive. HAPS 80D from Synopsys delivers a complete hardware and software prototyping solution right to your desk. In this episode of Chalk Talk, Amelia Dalton chats with Neil Songcuan of Synopsys about the … Read More → "HAPS-80 Desktop Prototyping Solution"
Moving to 48V — Mouser Electronics and Vicor   48V power supplies have numerous advantages over lower voltage systems. With 48V you can deliver more power more efficiently in a smaller form factor. In this episode of Chalk Talk, Amelia Dalton talks with Robert Gendron and Ian Mazsa of Vicor about advantages and tips for designing higher-voltage power systems. Click here for … Read More → "Moving to 48V — Mouser Electronics and Vicor"
MLCC Alternatives   The current shortage of multi-layer ceramic capacitors (MLCCs) is impacting a lot of project schedules. If you want to be sure your project isn’t hit by long MLCC lead times, and you’d like to improve a few things at the same time, there are some superb alternatives now on the market. In this … Read More → "MLCC Alternatives"
Maxim’s Himalaya uSLIC Solution: Industry’s Smallest Power Modules – Mouser and Maxim Integrated   New ultra-small power modules can deliver smaller solution size, higher reliability, and higher power density. In this episode of Chalk Talk, Amelia Dalton chats with John Woodward from Maxim Integrated about the industry’s smallest power modules. They might be exactly what you need for your next design. Click here for more information about … Read More → "Maxim’s Himalaya uSLIC Solution: Industry’s Smallest Power Modules – Mouser and Maxim Integrated"
Scaling Up Vision and AI DSP Performance  For high-performance, low-power processing of AI and machine vision algorithms, latency can be critical. In this episode of Chalk Talk, Amelia Dalton chats with Pulin Desai from Cadence Design Systems about the using the new Vision Q6 processor core for embedded vision and AI applications. Click here for more information about Vision DSPs for … Read More → "Scaling Up Vision and AI DSP Performance"
KSIM: Capacitors – Mouser and KEMET  Finding the right capacitor for your design can be a challenge. Many designers don’t take the time to research the best capacitor for their application, and this can result in increased cost, reduced performance, and reduced reliability. In this episode of Chalk Talk, Amelia Dalton chats with Wilmer Companioni of KEMET about KSIM – … Read More → "KSIM: Capacitors – Mouser and KEMET"