Max 10 Kills the CPLD

Altera Redefines Non-volatile FPGAs

by Kevin Morris

The venerable CPLD (Complex Programmable Logic Device), forefather of today’s flourishing FPGA and programmable logic industry, died peacefully in its sleep last night of natural causes. No memorial services are planned. The CPLD is survived by an incredible array of modern, capable devices that take the concept of programmable hardware to places never envisioned by the stately senior sum-of-products statesman.

If you visit the Wikipedia page for “CPLD” you will find a picture of an Altera MAX device (EPM7128), a 2,500 gate-equivalent, 128 macrocell “second generation” CPLD (or “EPLD” as the company was spinning it in those days) which, according to the datasheet, was capable of implementing “complete system-level designs.” That is, of course, if you were designing a “system” that could be implemented in well under 2,500 gates, was all digital, and had a 2-digit number of IOs.  Read More


Industry News

September 30, 2014

TSMC and Synopsys Accelerate Custom Design Productivity for 16FF+ Process

Synopsys Announces New Additions to Liberty to Significantly Speed up Timing Closure

IAR Systems dominates the tools market for ARM Cortex-M with leading code efficiency

ATopTech’s Physical Implementation Tools Certified to Support Advanced Designs in TSMC’s 16nm FinFET+ Process

September 29, 2014

Coverity Launches Code Spotter™ in Free Beta Version to Speed Defect Detection in Java Code

Renesas Electronics Expands True Low Power™ RX111 Group Microcontroller Lineup within the 32-Bit RX Family with Larger Memory Capacities up to 512 KB

Cadence IP Portfolio and Tools to Support New TSMC Ultra-Low Power Technology Platform

ARM and Synopsys Expand Collaboration to Improve Quality of Results and Time-to-Results for Leading-Edge ARMv8-A and ARMv7-A Cores

Microsemi Expands Customer Application Design Opportunities by Introducing SmartFusion2 Advanced Development Kit with Largest Density 150K LE Device

Cadence and ARM Expand System-on-Chip Design Collaboration with New Multi-Year Technology Access Agreement

S2C Announces AXI-4 Prototype Ready Quick Start Kit

September 26, 2014

Eurotech Announces Release of Kura 1.0 Java-OSGi Framework for M2M Gateways and Smart Sensor

Versatile Media Isolated Pressure Sensor from Measurement Specialties Withstands Extremely Corrosive Environments

VadaTech Offers Hybrid 2U MicroTCA Chassis Platform with Rear Transition Slots

High-Speed 5 GS/s PCIe Digitizer Cards released by Spectrum

Cadence Digital and Custom/Analog Tools Achieve TSMC Certification for 16FF+ Process

September 25, 2014

Tiny Balun-on-a-Chip from STMicroelectronics Simplifies Bluetooth Smart® Design

Valencell Opens New State of the Art Sports Testing Lab to Support the Development and Validation of Highly Accurate, Precise Biometric Wearables

Zuse Institute Berlin reduces debugging time on enterprise software research projects with UndoDB

Telit Introduces Jupiter SL869-V2S GPS Module

Grenoble Hosting SEMICON Europa Oct. 7-9, First Time Event Held in France

Saelig Introduces Device For Safety Measuring High Voltage Power Transistors with Oscilloscopes

New development system includes real-time hardware debug, industrial Ethernet and Fieldbus capabilities

KLA-Tencor to Present on Intelligent Feed-Forward of Non-Litho Errors for 3D Patterning at the APC Conference

Small Footprint Boost Controller from Diodes Incorporated Simplifies LED Backlighting

New Amplicon embedded PC offers maximum PCI/PCIe expansion flexibility in fanless compact design

Dynamic Vibration Sensor Easily Connects via USB to Smart Phones, Tablets and PCs

Renesas Electronics Delivers Improved Safety, Efficiency and Affordability for Small Appliances and Consumer Products with Expanded Brushless DC Motor Control Support

News Archive

Expanding EDA

Newer Tools Let You Do More than Just Electronics

by Bryon Moyer

The Beat Goes On

The Cadence of IoT and the Sound of a Single Atom

by Amelia Dalton

The Four Horsemen

What Does the Future Hold for the Semiconductor Industry?

by Dick Selwood

Prpl With Envy

Foundation Aims to Prevent MIPS Fragmentation

by Jim Turley

Articles Archive

 

EEJournal On The Scene Video News
 Hosted by Amelia Dalton

editors' blog

Collocated Location Technology

posted by Bryon Moyer

Broadcom brings GNSS and inertial sensors together on a single chip. (Yesterday)

Just What Is the New IEEE Sensor Standard?

posted by Bryon Moyer

IEEE and MIG announced a sensor standard. Depending on what you read, it is about a bunch of different things. Most of which it isn’t really about. Not directly, anyway. (25-Sep)

Turning InGaAs on its Head

posted by Bryon Moyer

Leveraging the cost-effectiveness of silicon for high-performance materials (23-Sep)

M2M in Orbit

posted by Bryon Moyer

Taoglas provides satellite Thing connectivity. (18-Sep)

ProbMe Simplifies Thing WiFi Connection

posted by Bryon Moyer

Some Things are harder to connect to WiFi than your phone or computer. ProbMe tries to make it easier. (16-Sep)

Editors' Blog Archive

 

forum

Max 10 Kills the CPLD

Posted on 10/01/14 at 3:12 AM by juergenuk

juergenuk
@Steve DevKits are mostly subsidized, so does not count. I meant designed in, product cost, how does it compare Altera - Lattice - Microsemi - Xilinx imlementation ( sorry if I forgot some ). I know there are many variants - any example/volume appreciat…

Expanding EDA

Posted on 09/30/14 at 10:10 PM by Kev

Given that the EDA guys are a rather non-"Agile" bunch I'm not sure they're going to get much done.

Personally I think you can re-apply a lot of EDA tools aimed at hardware design at parallel software design. Parallel stuff is hard to debug, so formal …

Max 10 Kills the CPLD

Posted on 09/30/14 at 11:38 AM by SteveCasselman

@juergenuk You can buy a development board with the largest part for $50. The smallest part is 25 times smaller and yet is still large enough to fit a NIOS processor and 16 DSP units plus logic left over.

Max 10 Kills the CPLD

Posted on 09/30/14 at 11:10 AM by juergenuk

juergenuk
I am missing where this new Altera series fits price wise. Lattice never went to the biggest - but instead a market not so much served by A and X. I have been selling against A and X - or more positively, finding the right niches for Lattice.
So Lattice …

Expanding EDA

Posted on 09/29/14 at 9:57 AM by bmoyer

bmoyer
What do you think about the cycles of EDA and EDA's expanding scope?

Who Controls the Power?

Posted on 09/29/14 at 2:11 AM by GuidoGam

Not a single word about Alpha?

There’s a Processor in My FPGA!

Posted on 09/28/14 at 10:35 PM by JohnSwan

JohnSwan
Indeed, Mentor Graphics had the ASAP (Application Specific Assistant Processor)tool 10 years ago. It automated the ability for the user to select a function and push it onto the FPGA fabric. It used an HLS tool of course for the synthesis. Though OpenCL g…

The Four Horsemen

Posted on 09/25/14 at 12:05 PM by Dick Selwood

Dick Selwood
Are we just muddling along? Are we about to stall?

IoT Standards

Posted on 09/22/14 at 5:19 PM by bmoyer

bmoyer
Thanks for the link, Will. I'll look into it.

Forum Archive

subscribe to our weekly newsletters

twitter.png   rss.png    googleplus.png    linkedin.png    youtube.png    facebook.png



On Demand Archive

 Watch Chalk Talks
 On our New EE Journal YouTube Channel
 Hosted by Amelia Dalton

chalk talks

High Speed Data Acquisition and Software Defined Radio Made Simple

Building a hybrid computing platform from scratch is a huge and complicated project. Luckily, somebody has already done that work for you. In this episode of Chalk TalkHD Amelia chats with Justin Braun (4DSP) about how you can use pre-designed platforms to dramatically simplify these complex computing and data acquisition problems.

Maximize Design Productivity With PCIe/104 FPGA/Processor

In this episode of Chalk TalkHD Amelia chats with Christine Van De Graaf of Kontron, who explain how Kontron is incorporating pre-made, small form factor boards, a high-performance embedded processor programmable logic into their new MSMST board and how we can get started designing with one.

Spartan-6 FPGAs in Video Designs

In this episode of Chalk TalkHD, Amelia chats with Tom Hill and Maureen Smerdon of Xilinx about how Spartan-6 FPGAs can accelerate your next video design, and how adding embedded vision to those designs is getting easier and easier.

Rigid-Flex and Embedded Components

These days, flexibile circuit boards are making their way into the mainstream. Rigid-flex design gives us all kinds of new capabilities in form factor, as well as the opportunity to replace expensive and unreliable cables and connectors. But, how do you handle rigid-flex PCB design in your layout tools? In this episode of Chalk Talk, Amelia Dalton chats with Altium's Ben Jordan about rigid-flex design in Altium Designer - and how you can use those same capabilities for embedded components as a bonus!

OpenCL on FPGAs: Accelerating Performance and Design Productivity

FPGAs have amazing capabilities when it comes to accelerating performance-critical algorithms at a tiny fraction of the power it would require to run them in software. The marriage of FPGAs with conventional CPUs could provide a truly remarkable high-performance computing platform. However, the problem has always been how to program it. In this episode of Chalk TalkHD Amelia chats with Albert Chang of Altera about about how OpenCL can now be used to program FPGAs. OpenCL is already very popular for programming systems with graphics processors (GPUs). Now, Altera has enabled us to use this same language to program FPGA+CPU systems.

Abstract and Conquer: A New Alternative to Hierarchical Timing Analysis

Sign-off timing analysis for today’s complex SoC designs can be daunting. Rather than just throwing more computer power at the problem, you need to adopt a hierarchical approach and take advantage of higher levels of abstraction. In this episode of Chalk Talk, Amelia Dalton talks with Ruben Molina of Cadence Design Systems about a new, faster approach to sign-off timing analysis.

Solving the 100Gbps Challenge with ABAX2

What do you do when plain-old FPGAs leave too much on the table to handle your next bandwidth challenge efficiently? In this episode of Chalk TalkHD Amelia chats with Christian Plante (Tabula) about Tabula's new ABAX2 devices - based on their innovative Spacetime architecture. ABAX2 is fabricated on the latest Intel 22nm Tri-Gate technology, and can give you an enormous advantage in your next 100G design.

Chalk Talk Archive


Login Required

In order to view this resource, you must log in to our site. Please sign in now.

If you don't already have an acount with us, registering is free and quick. Register now.

Sign In    Register