Racing Electronics
One of the perks of writing about electronics is that you get to see some really cool stuff. And while motor racing is not at the top of my list of enthusiasms, an invitation by Freescale to visit the McLaren Technology Centre was just too good to pass up. Besides which, it turned my fellow hacks on EE Journal green with envy: there are some real petrol heads, including a race driver and a Formula 1 Fanatic.
The reason for the invitation is that Freescale’s processors are the intelligence in the engine control units (ECU) that McLaren supplies, on an exclusive basis, to the IndyCar, NASCAR and Formula 1 (F1) racing series. Read More
Industry News
May 16, 2012
3M Technology Enables Ultra Low Power All-in-One Smart Zero Client from HP
Advantech MI/O-Compact SBC MIO-5250 Powered by Intel® Atom™ Ultra Low Power Dual Core Processor
Alpha Data Releases NEW High-Performance Kintex-7 FPGA Based XMC Card
EVE Unveils 10-Gigabit Ethernet Validation Platform
VideoPoster-III from Distec Displays Images and Full-HD Videos
Carbon Design Systems Unveils Off-the-Shelf Performance Analysis for ARM Cortex-A Processors
EVE Adds New Applications for Leading SoC Emulation Platform Environment
RFFM7600 5.0V, 2.5GHz TO 2.7GHz High Power Front End Module
IC Manage Releases 4th Annual Global Design Management Survey Results
New IC-output optocouplers from Renesas Electronics with extra-long creepage distance of 14.5 mm
May 15, 2012
Molex Unveils Two New Versions in its Premo-Flex™ Line of Jumpers
Forte’s SystemC High-Level Synthesis Licensed by HighIP Design Company
Digi-Key Corporation and T-Global Technology Sign Global Distribution Agreement
Crucial LRDIMM Server Memory Now Available To Support New Intel Xeon Processor E5 Family
Cadence Introduces New NVM Express IP Solutions for Solid State Storage Applications
May 14, 2012
New Release of ITTIA DB SQL Offers More Choice to Embedded/Mobile Software Developers
Sigrity Introduces XcitePI Chip IO Interconnect Model Extraction and Assessment Tool
Chomerics Europe starts production at its advanced shielded cast window manufacturing cell
Satin Technologies to Introduce Automated Design Monitoring at DAC 2012
MIPS Plants a New Family Tree
“Aptiv” Line of Processors: the Start of a New Generation
The Process of Process Tracking
Satin Attempts to Corral a Recalcitrant Beast
Springtime in the SoC
Audio IP, Static Analysis and Board Member Switch-a-roo
An EDA Foil Hat
iROC Attacks Cosmic Attacks
editors' blog
Cadence Supports NVMe
Last year’s new standard for connecting non-volatile memory via PCIe is now available in IP from Cadence. (Today)
Graphene Quilts
UC Riverside researchers come up with a way to remove heat from GaN circuits. (10-May)
Powering Up Power Analysis
Apache addresses power analysis of 3D ICs and sub-20-nm behemoth chips. (8-May)
FPGA Prototype Debug Access
Synopsys tries to ease the tradeoff between trace capture speed and FPGA resource utilization. (7-May)
The New (Pro)Vocative
The New (Pro)Vocative @Readers: There’s a new way to be cool: constantly show the world that you use Twitter or know people that use Twitter or just notice that @ sign all over the place and figured out how to use it. 1 (7-May)
forum
Racing Electronics
Posted on 05/16/12 at 1:22 PM by Jim Turley
MIPS Plants a New Family Tree
Posted on 05/15/12 at 5:17 PM by kevin
The Process of Process Tracking
Posted on 05/15/12 at 3:01 PM by Jim Turley
Oh, wait... It's Satin, not Satan.
Never mind.
MIPS Plants a New Family Tree
Posted on 05/15/12 at 2:59 PM by Jim Turley
MIPS Plants a New Family Tree
Posted on 05/15/12 at 11:25 AM by kevin
MIPS could now come out with a series of passive comp…
The Process of Process Tracking
Posted on 05/14/12 at 1:25 PM by bmoyer
Springtime in the SoC
Posted on 05/12/12 at 2:23 AM by caccolillou
Thanks to its accelerometers I could measure every aspect about one's strides.
The low power fram could be used to log every aspect of your performances (strides made,speed,envir…
Springtime in the SoC
Posted on 05/11/12 at 1:58 PM by amelia
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On Demand
Catapult C Synthesis Designing a JPEG Compression Engine
Chalk Talk sponsored by Mentor Graphics
Plug & Play Signal Integrity for High-Performance FPGAs with Transceivers
See 100G Interlaken Solution on 40-nm High-Density FPGA
Putting Low Power and Flexibility Where It Matters Most: Handheld Portable Applications
White Paper sponsored by Microsemi
Reduce Total System Cost in Portable Applications Using MAX II CPLDs
White Paper sponsored by Altera
Accelerating DSP Designs with the Total 28-nm DSP Portfolio
White Paper sponsored by Altera
Designing with Multiple Industrial Ethernet Standards on a Single Hardware Platform
Easily Support WDR CMOS Image Sensor Processing with Low-Cost FPGAs
Cut DSP Development Time – Get High Performance From C, No Assembly Required
White Paper sponsored by Tensilica
Designing an IP Camera with a Single, Low-Cost FPGA
Scalable Smart Debugging With ZeBu-Server
Chalk Talk sponsored by EvE
Implementing Video Display Interfaces Using MachXO2 PLDs
White Paper sponsored by Lattice
3 Reasons to Use FPGAs in Industrial Applications
chalk talks
Hierarchical Design Flows: Design Preservation & Team Design
In this episode of Chalk TalkHD, Amelia chats with David Dye of Xilinx about how Hierarchical Design methodologies and Team Design can accelerate your next FPGA design and get those team members of yours working productively together. With these tools and techniques, two million logic elements won't seem like that much after all.
Chalk Talk sponsored by Xilinx
Power Supply Management in High-Availability Systems
One of the most basic (and most often overlooked) aspects of high-reliability system design is getting reliable power to all of our components. We need the right kind of power at the right places - at the right times, and in the right order. We need to handle power-up, power-down, and reset cases (among others). It can be really complicated. In this episode of Chalk TalkHD, Amelia Dalton chats with Wendy Lockhart of Microsemi about how to handle power management for high-reliability systems.
Chalk Talk sponsored by Microsemi
High-Reliability in FPGA Design - SEU Mitigation
Neutrons are coming for you and you'd better be prepared. Whether we like it or not, SEUs (Single Event Upsets) are becoming a bigger and bigger problem for our designs, especially for high realibility systems. If you thought SEUs couldn't mess up your next design because you aren't designing something destined for space, you need to think again. In this episode of Chalk TalkHD, I chat with Jeff Garrison of Synopsys about the how we can battle SEUs (on the ground or in the air) with the latest generation of design tools.
Chalk Talk sponsored by Synopsys
FPGA Prototyping with the Kintex-7 KC705 Evaluation Kit
In this episode of Chalk Talk HD, Amelia chats with Evan Leal of Xilinx about their new Kintex-7 KC705 Evaluation Kit, all the cool stuff that’s included and how we can use it to speed up our FPGA Prototyping.
Chalk Talk sponsored by Xilinx
The Power of Tcl in PlanAhead
In this episode of Chalk TalkHD Amelia chats with Tori Darien from Xilinx about using Tcl in Xilinx’s PlanAhead tool for FPGA design. Amelia throws her some examples, and Tori walks us through how to work them using PlanAhead’s Tcl interface.
Chalk Talk sponsored by Xilinx