How Wearables Will Revolutionize Prenatal Medicine
In this week’s Fish Fry we explore a whole new world of wearable technologies with Julian Penders from Bloom Technologies. Julian (co-author of “Wearable Technologies for Healthier Pregnancies”) and I talk about how wearable technologies can help monitor lifestyle behaviors. We’ll be looking at the future of wearable technologies targeted for pregnancy, and discussing how these technologies pose additional challenges. Also this week, I check out Cadence’s new Innovus tool suite and reveal how it could make routing your million gate IC design just a little bit easier. Read More
July 03, 2015
July 02, 2015
July 01, 2015
June 30, 2015
June 29, 2015
New Bitcode Format Could Be the First Step Toward CPU-Neutral Platforms
Patent Law is a Slippery Slope for Engineers
Hints of Solutions to Come
Seeking EDA Gold (and Answers) with Xerxes Wania
posted by Bryon Moyer
Mentor has consorted (carefully) with a competitor to provide a path to faster RTL power analysis. (18-Jun)
posted by Jim Turley
Apple's new "Bitcode" software-distribution mechanism lays the groundwork for a switch in CPU architecture, operating system, or both. (18-Jun)
posted by Bryon Moyer
Ayla Networks wants to make it easier for you to build a phone app that will talk to your IoT widget. (16-Jun)
posted by Dick Selwood
EDA Playground has a new toy (12-Jun)
posted by Bryon Moyer
What’s the big deal with Big Data? (11-Jun)
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Solar Impulse plane lands in Hawaii (Yesterday)
A robot is the star of new opera (30-Jun)
Featured Chalk Talk
When it comes to PCB Design, the giant companies don't get ALL the cool toys. Desktop design tools are now getting impressive capabilities that rival their enterprise-scale big brothers. In this episode of Chalk Talk, Amelia Dalton talks with Jim Martens of Mentor Graphics about the new PADS VX and the impressive capabilities it brings to desktop electronic design.
USB Type-C is coming, but how will you add it to your design? In this episode of Chalk Talk, Amelia Dalton chats with Gordon Hands of Lattice Semiconductor about a great new flexible solution for USB Type-C. Your job may be easier than you think.
Even the best "plug and play" IP blocks are far from fool-proof. One of the most challenging aspects of IP-based design can be getting the blocks stitched together properly, making sure you have the right version of all the IP blocks, and confirming the configuration of your whole design. In this episode of Chalk Talk, Amelia Dalton chats with Tim Vanevenhoven about the powerful correct-by-construction automation built into the IP Integrator in Vivado Design Suite from Xilinx. IP Integrator seriously raises the bar on automation of IP-based design.
When you're using a new tool for the first time, a good GUI is great to have, but once you're up and running and automating a complex design process, scripted flows offer a much more powerful means of controlling your tools. In this episode of Chalk Talk, Amelia Dalton and Ron Plyler of Xilinx explore scripted flows in the Vivado design suite.
Synthesis is the single most important step in creating a high-quality implementation of our design. But, we can't expect our synthesis tool to produce the best results without considering the very important effects of routing delay introduced by placement and routing. In this episode of Chalk Talk, Amelia Dalton talks with David Stratman of Cadence about how to apply physically-aware synthesis techniques to improve the overall quality of your design.
Sign-off timing analysis for today’s complex SoC designs can be daunting. Rather than just throwing more computer power at the problem, you need to adopt a hierarchical approach and take advantage of higher levels of abstraction. In this episode of Chalk Talk, Amelia Dalton talks with Ruben Molina of Cadence Design Systems about a new, faster approach to sign-off timing analysis.
Ever notice how hard it can be to get the full utilization that an FPGA datasheet promises? Xilinx is aiming to change all that. In this episode of Chalk Talk, Amelia Dalton talks with Darren Zacher of Xilinx about the new Ultrascale FPGA family, and how the architecture has been optimized for maximum utilization.