The Smartest Socks on the Block

Let’s Get Physical with Sensoria

by Amelia Dalton

Your heart is pounding. Your iTunes playlist is nearing its end. The final mile is at hand and you couldn’t be happier. What if you could make your morning run smarter? In this week’s Fish Fry, we investigate sensor-enhanced fabrics from IoE (Internet of Everybody) company Sensoria that aims to do just that. Davide Vigano (Co-Founder - Sensoria) and I delve into in the details of Sensoria’s wide range of high tech fitness products, and reveal how Sensoria can help you make your own MEMS-enhanced fabrics. Also this week, we check out a new design competition recently launched by NASA and America Makes where you can help design (and build) a 3-D printed space colony for MARS (and make some serious cash while doing it).  Read More

Industry News

May 22, 2015

Pentek Introduces Slimmed Down and Featured Up 200 MS/sec Rugged Portable RF/IF Signal Recorder

Altium Adds New Extension to Flagship PCB Design Tool for Seamless SOLIDWORKS(r) Collaboration

May 21, 2015

Cadence Strengthens Allegro Technology Portfolio To Make Design Cycles Shorter and More Predictable

Quantum Materials to Announce New Class of High-Reliability Quantum Dots at SID Display Week 2015

Real Intent Delivers Major Innovation in Clock Domain Crossing Sign-off of SoC Designs

HeliaFilm® on concrete façade

Excelsys Xsolo Power Supplies Meet Medical Performance Specifications

Agnisys Unveils Software to Automate Register Verification Process for SoC, IP, FPGA Designs

Applied Materials’ Breakthrough Patterning Hardmask Enables Copper Interconnect Scaling

Synopsys Announces Industry's Lowest Power PCI Express 3.1 IP Solution for Mobile SoCs

May 20, 2015

Sensoria Partners With Athletes for Charity on Clothing Drive for Disadvantaged Youth in Haiti

STMicroelectronics and Paradox Engineering Present Smart City Technologies at TECHNO-FRONTIER 2015

Latest version of Java SE 8 now available for MIPS

ams launches next-generation NFC interface tag IC with advanced data and energy management features

IAR Systems boosts 8051 development targeting Internet of Things

Lose power, not data. New ultra-low-power FRAM microcontrollers from Texas Instruments revolutionize context save and restore.

May 19, 2015

Imec and Lam Research Corporation Develop Novel Metallization Method

MAZeT amplifies signals delivered by optoelectronic sensors

DIN rail DC-DC converters offer a wide input and noise immunity for industrial applications

Innovasic Demonstrates “In-Line” Security for the Industrial Internet of Things

UltraSoC and Teledyne LeCroy collaborate to unify debug and validation for system designers

STMicroelectronics First Past the Post with Automotive-Grade 1200V Thyristor for Ultra-Reliable Power Control

Hoffmann-Krippner To Roll Out New Sensor Technologies at Sensors Expo

Automotive 2A, 70V SEPIC/Boost/ Converter with 9µA Quiescent Current Includes Power-On Reset & Watchdog Timer

Anritsu Introduces 4-port Broadband VNA System with Industry’s Widest Frequency Coverage from 70 kHz to 110 GHz

HUBER+SUHNER provides live demonstrations of termination techniques affiliated with “EACON” field-mountable cable assembly products at IMS 2015

Cree 12GHz GaN HEMT-based MMICs Now at Mouser

May 18, 2015

Fairchild’s Tiny, Low-Power USB Type-C Solution Makes Debut in LeTV’s New Smartphone Family

News Archive

A Dendrite-Free Lithium Anode

Better Batteries Without the Fireworks

by Bryon Moyer

Buses, Windows, and You

Where is the Real Value in Embedded Engineering?

by Jim Turley

The Hardware Vanishing Point

Someday, Will it All be Software?

by Kevin Morris

A Stictionless NEMS Switch

Or, as MIT Calls It, a Squitch

by Bryon Moyer

Articles Archive


Featured Video

editors' blog

Cadence’s Faster Debug Idea

posted by Bryon Moyer

Indago promises to allow debug without having to run verification multiple times to zero in on a bug. (19-May)

Faster NoC Tuning

posted by Bryon Moyer

Arteris says it has a way to get your NoC optimized faster than how you’ve been doing it. (12-May)

Sensor Hub Power Drops Again

posted by Bryon Moyer

QuickLogic has dropped the power floor for sensor hubs with their ArcticLink 3 S2 LP. (5-May)

Intel/Altera Agreement (Partially) Tells the Tale

posted by Kevin Morris

We did a lot of speculation in our recent articles about the rumored Intel bid to buy Altera. One of the areas of most intense speculation was the 2013 agreement the two companies signed - for Intel to manufacture 14nm FPGAs for Altera. More than two years after that deal was signed, Intel is rumored to be making an offer to buy Altera for upwards (maybe far upwards) of $10B. But, is the existing 2013 agreement potentially weakening Intel’s bargaining position? (4-May)

Vertically Integrated BLE Module

posted by Bryon Moyer

Cypress says that it’s iffy for small, low-volume companies to do their own RF. And buying existing modules leads to support issues. And they say they have an answer. (30-Apr)

Editors' Blog Archive



Buses, Windows, and You

Posted on 05/22/15 at 5:40 AM by Dick Selwood

Dick Selwood
Amazon Prime started as just free shipping. Now they have seriously upped the subscription and thrown in Amazon instant video streaming. Cool if you watch lots of video but not if you only want books. Strangely it allows you to opt out of free delivery bu…

A Dendrite-Free Lithium Anode

Posted on 05/21/15 at 10:43 AM by bmoyer

What do you think of the higher-concentration LiFSI-DME battery electrolyte?

Eschew the Real World

Posted on 05/20/15 at 11:28 AM by TotallyLost

I understand simulating a CPU for a complex SoC in an attempt to get early code development on low level memory and device interfaces ... in particular to have bring up diagnostics done by the time silicon and boards finally arrive.

As obruend notes, t…

Eschew the Real World

Posted on 05/20/15 at 12:19 AM by obruend

I do not really see the upside of simulating a CPU on another CPU for most projects (sure, there may be exceptions). Software development can easily be started before any hardware is available by just compiling the code to a hardware which is already avai…

The Hardware Vanishing Point

Posted on 05/19/15 at 4:21 PM by TotallyLost

I don't think it's anywhere near that gloomy for Moore's law and new innovation.

Consider that most of the devices we have today, where not imagined 50 years ago in the form and utility they have taken on. Sure Dick Tracy had a watch phone, but few act…

Crack a combination lock in 30 seconds with this 3D-printed contraption

Posted on 05/18/15 at 12:56 PM by RyanKenny

Very clever. Except that it only seems to work on a lock that is not actually 'locking' anything...

A Stictionless NEMS Switch

Posted on 05/18/15 at 10:05 AM by bmoyer

What do you think about MIT's stictionless switch?

Intel and Altera – Eleven-Figure Chicken

Posted on 05/15/15 at 10:08 AM by TotallyLost


I agree that there are a number of designs that will push the boundaries, and break any tool -- software or hardware tools.

We had the same problem with software tool maturity porting applications to new machines/architectures running Unix, …

Eschew the Real World

Posted on 05/14/15 at 3:23 PM by TotallyLost

This article probably gets a lot of laughs from less thoughtful arrogant hardware types.

The stereotype BS is just another form of racism, that does NOTHING for building teams.

The challenge is to get hardware types to accept broad undefined moving …

Forum Archive

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Featured Chalk Talk

On Demand Archive

chalk talks

Static Timing Analysis and Constraint Validation

Before you can even think about timing closure in your FPGA design, you have to set up timing constraints. But, being sure that you have the right constraints can be a real challenge. In this episode of Chalk Talk, Amelia Dalton chats with Ron Plyler of Xilinx about some powerful new ways to set up and validate timing constraints on your way to timing closure with Xilinx's Vivado tool suite.

Model-Based Design for Xilinx Zynq & Altera SoC Devices

You'll get way more out of your Xilinx Zynq or Altera SoC device if you have a smooth design flow from MATLAB and Simulink. Luckily, MathWorks has already thought of that. In this episode of Chalk Talk, Amelia Dalton chats with Eric Cigan of MathWorks about Model-Based Design for this new powerful class of programmable devices.

Vivado IP Integrator

Even the best "plug and play" IP blocks are far from fool-proof. One of the most challenging aspects of IP-based design can be getting the blocks stitched together properly, making sure you have the right version of all the IP blocks, and confirming the configuration of your whole design. In this episode of Chalk Talk, Amelia Dalton chats with Tim Vanevenhoven about the powerful correct-by-construction automation built into the IP Integrator in Vivado Design Suite from Xilinx. IP Integrator seriously raises the bar on automation of IP-based design.

Increase FPGA Performance with Enhanced Capabilities of Synplify Pro & Premier

The most important factor in getting great performance from your FPGA design is optimization in synthesis and place and route. In this episode of Chalk Talk, Amelia Dalton chats with Paul Owens of Synopsys about the latest techniques for getting the most performance out of your design tools, and therefore out of your FPGA design.

Vivado In-System Debug

Today's complex FPGA designs can be challenging to debug. If you're debugging in hardware, you need both visibility and control of what's going on inside your chip. In this episode of Chalk Talk, Amelia Dalton talks to Ron Plyler of Xilinx about doing hardware debug in Xilinx's Vivado tool suite.

4-Channel Analog Front End Solution

Designing the analog front end for any project can be a time-consuming engineering task. And, without a lot of analog expertise, many of us will face some tricky engineering challenges. In this episode of Chalk Talk, Amelia Dalton chats with Bill Laumeister of Maxim Integrated about a new analog front end (AFE) that both simplifies and improves the design of many analog front ends.

Architecture Matters: Three Architectural Insights for SoC FPGAs

New devices that combine the power and flexiblility of FPGAs and conventional processors on a single chip represent a breakthrough in capability. But, understanding the complex architecture of these sophisticated components requires us to look under the hood to see how the architecture fits our design requirements, and how to choose the right chip for our application. In this episode of Chalk Talk, Amelia Dalton talks with Todd Koelling of Altera about what to look for in the architecture of your SoC FPGA.

Chalk Talk Archive

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