fish fry
Subscribe Now

sensAI and Sensibility

Designing AI on the IoT Edge with Lattice’s sensAI Technology Stack

“Success is where preparation and opportunity meet.” – Bobby Unser

Many of us would love to get started on an artificial intelligence-enhanced IoT edge device design but we’re not sure how to get started. In this week’s episode of Fish Fry, I sit down with Deepak Boppana and we talk about a new technology stack unveiled by Lattice Semiconductor called sensAI. Deepak and I explore the details of the sensAI technology stack and why the power and cost components of this stack set it apart from other solutions. Also this week, we investigate how China is aiming to be the world leader in artificial intelligence by 2030 and how they are using AI and facial recognition in their school system today.

Download this episode (right click and save)

Links for June 1, 2018

More information about the Lattice sensAI Stack

Ultra-Low Power Lattice sensAI Leads Mass Market Enablement of Artificial Intelligence in Edge Devices

New Feature Article by Kevin Morris: More AI at the Edge – Lattice Launches sensAI Stack

China wants to be a $150 Billion World Leader in AI in Less Than 15 Years (CNBC)

Chinese School uses Facial Recognition to Make Kids Pay Attention

New Episode of Chalk Talk: Deep Learning with MATLAB

Click here to check out the Fish Fry Archive.

Click here to subscribe to Fish Fry via Podbean

Click here to get the Fish Fry RSS Feed

Click here to subscribe to Fish Fry via iTunes.

Fish Fry Executive Interviews

Darrin Billerbeck, CEO – Lattice Semiconductor

Anupam Bakshi, CEO – Agnisys

Dave Kleidermacher, CTO – Green Hills Software

Robert Blake, CEO – Achronix

Jack Harding, CEO – eSilicon

Michiel Ligthart, COO – Verific

Adnan Hamid, CEO – Breker Technologies

Jeff Waters, VP and General Manager – Altera

Simon Davidmann, CEO – Imperas

Ted Miracco, CEO – SmartFlow Compliance Solutions

Jessica Gomez – Rogue Valley Microdevices

Shishpal Rawat, Chairman – Accellera Systems Initiative

Kevin Bromber, CEO – myDevices

Daniel Hansson, CEO – Verifyter

Mark Papermaster, CTO – AMD

David Fried, CTO – Coventor

Dr. Steven LeBoeuf, President – Valencell

David Dutton, CEO – Silvaco

Bob Niemiec, CEO – TwistThink

Allan Martinson, COO – Starship Technologies

Zhihong Liu, Chairman and CEO – ProPlus Solutions

Taher Madraswala, CEO and President – Open-Silicon>

Kapil Shankar, CEO and Director – AnDAPT

Dan Fox, CTO – Local Motors

Leave a Reply

featured blogs
Jun 22, 2021
Have you ever been in a situation where the run has started and you realize that you needed to add two more workers, or drop a couple of them? In such cases, you wait for the run to complete, make... [[ Click on the title to access the full blog on the Cadence Community site...
Jun 21, 2021
By James Paris Last Saturday was my son's birthday and we had many things to… The post Time is money'¦so why waste it on bad data? appeared first on Design with Calibre....
Jun 17, 2021
Learn how cloud-based SoC design and functional verification systems such as ZeBu Cloud accelerate networking SoC readiness across both hardware & software. The post The Quest for the Most Advanced Networking SoC: Achieving Breakthrough Verification Efficiency with Clou...
Jun 17, 2021
In today’s blog episode, we would like to introduce our newest White Paper: “System and Component qualifications of VPX solutions, Create a novel, low-cost, easy to build, high reliability test platform for VPX modules“. Over the past year, Samtec has worked...

featured video

Reduce Analog and Mixed-Signal Design Risk with a Unified Design and Simulation Solution

Sponsored by Cadence Design Systems

Learn how you can reduce your cost and risk with the Virtuoso and Spectre unified analog and mixed-signal design and simulation solution, offering accuracy, capacity, and high performance.

Click here for more information about Spectre FX Simulator

featured paper

An FPGA-Based Solution for a Graph Neural Network Accelerator

Sponsored by Achronix

Graph Neural Networks (GNN) drive high demand for compute and memory performance and a software only based implementation of a GNN does not meet performance targets. As a result, there is an urgent need for hardware-based GNN acceleration. While traditional convolutional neural network (CNN) hardware acceleration has many solutions, the hardware acceleration of GNN has not been fully discussed and researched. This white paper reviews the latest GNN algorithms, the current status of acceleration technology research, and discusses FPGA-based GNN acceleration technology.

Click to read more

featured chalk talk

FPGAs Advance Data Acceleration in the Digital Transformation Age

Sponsored by Achronix

Acceleration is becoming a critical technology for today’s data-intensive world. Conventional processors cannot keep up with the demands of AI and other performance-intensive workloads, and engineering teams are looking to acceleration technologies for leverage against the deluge of data. In this episode of Chalk Talk, Amelia Dalton chats with Tom Spencer of Achronix about the current revolution in acceleration technology, and about specific solutions from Achronix that take advantage of leading-edge FPGAs, design IP, and even plug-and-play accelerator cards to address a wide range of challenges.

Click here for more information