At what point in the creation of a chip does physical design actually begin? (Spoiler Alert: answers may vary.) In this week’s episode of Fish Fry, Dave Stratman and I discuss the ongoing challenges of the physical design process, why convergent design flows are critical for today’s ever shrinking process nodes, and how form factor and the environment around the end customer affects physical design. We also check out the details of the world’s first 3nm test chip rolled out by Imec and Cadence Design Systems this week.
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Links for March 2, 2018
More information about Digital Design and Signoff (Cadence Design Systems)
Imec and Cadence Tape Out Industry’s First 3nm Test Chip
Fish Fry Executive Interviews
Darrin Billerbeck, CEO – Lattice Semiconductor
Dave Kleidermacher, CTO – Green Hills Software
Michiel Ligthart, COO – Verific
Adnan Hamid, CEO – Breker Technologies
Jeff Waters, VP and General Manager – Altera
Simon Davidmann, CEO – Imperas
Ted Miracco, CEO – SmartFlow Compliance Solutions
Jessica Gomez – Rogue Valley Microdevices
Shishpal Rawat, Chairman – Accellera Systems Initiative
Kevin Bromber, CEO – myDevices
Daniel Hansson, CEO – Verifyter
Dr. Steven LeBoeuf, President – Valencell
Allan Martinson, COO – Starship Technologies
Zhihong Liu, Chairman and CEO – ProPlus Solutions
Taher Madraswala, CEO and President – Open-Silicon>
Kapil Shankar, CEO and Director – AnDAPT
Kim Rowe, Founder and CEO — RoweBots
Lawrence Cooke, Founder and CEO — NovaSolix
Gregg Recupero, CTO — Performance-IP
Carl Alberty, Vice President – Cirrus Logic
Maximilian Odendahl, CEO — Silexica
Finbarr Moynihan, General Manager — MediaTek
Sanjay Pillay, CEO — Austemper
Harold Blomquist, CEO – Helix Semiconductor
Dale Dougherty and Sherry Huss, Co-Founders – Maker Faire
Chris Giovanniello, SVP and Co-Founder – Menlo Micro
