industry news
Subscribe Now

Achronix Speedcore Custom Blocks Supercharge Data Acceleration Systems

  • Speedcore custom blocks dramatically increase Speedcore eFPGA performance and reduce die area and power consumption
  • Fully supported in Achronix ACE design tools

Santa Clara, Calif., October 17th, 2017 – Achronix today announced the availability of Speedcore custom blocks for its eFPGA IP solutions. Achronix Speedcore eFPGAs accelerate data intensive AI / machine learning, 5G wireless, automotive ADAS, datacenter and networking applications. Speedcore custom blocks massively improve performance, power, and area; and enable functionality that has never before been possible in standalone FPGAs. With Speedcore custom blocks, customers gain ASIC efficiency while retaining FPGA flexibility, resulting in a highly efficient implementation that minimizes power and area while maximizing data throughput.

Traditional CPU-based architectures are not scaling to meeting the exponential growth in compute demand required by the new wave of intelligent data intensive applications. This demand is driving the need for new, heterogeneous compute architectures with programmable hardware accelerators. Speedcore eFPGAs deliver the highest performance and lowest cost hardware acceleration. Now with Speedcore custom blocks, functions that traditionally ran slowly and consume significant resources in standalone FPGA fabrics are optimized for maximum performance and minimal die area as illustrated in the following examples.

  • The area of a CNN-based YOLO object recognition algorithm was reduced by over 40% by optimizing the DSP and memory blocks for matrix multiplication.
  • Large string search functions that require parallel comparator arrays resulted in area reduction of over 90% when implemented in Speedcore custom blocks.
  • Barrel shifters and bit manipulation structures can be fully implemented in Speedcore custom blocks allowing larger, sophisticated applications in the same area, increasing the achievable frequency.
  • The core functionality of a 400 Gbps packet processing data path running at 800 MHz is implemented in Speedcore custom blocks with the programmable logic managing the analysis and control functionality. Today’s standalone FPGAs cannot support this high throughput for packet processing applications.

“Industry leaders are excited about Speedcore custom blocks and the potential they offer,” said Steve Mensor, Vice President of Marketing, Achronix Semiconductor. “The companies that we are working with are building the next generation of heterogeneous compute platforms and high-bandwidth communication systems. They are building high-performance hardware accelerators that can be changed over time as their compute algorithms evolve. Achronix eFPGA IP, now with Speedcore custom blocks, allows them to have programmability with ASIC-level performance and die size efficiency.”

Speedcore Custom Blocks Definition

Speedcore custom blocks are defined collaboratively by Achronix with its customers through a detailed architecture analysis of acceleration workloads. Repeated functions that are performance and/or area bottlenecks are evaluated as candidates to be hardened into Speedcore custom blocks. A new release of ACE design tools that includes the new Speedcore eFPGA with custom blocks is then provided to customers for benchmarking and evaluation. If required, the process is iterated to create the optimal solution for the customer’s system.

Support in ACE Design Tools

Achronix ACE design tools fully support Speedcore custom blocks from design capture to bitstream generation and system debug in the same way as memories and DSP blocks. Achronix creates a unique GUI for each Speedcore custom block that manages all configuration rules. ACE contains full timing details for all configurations of the Speedcore custom blocks, which allows ACE to complete timing-based place-and-route for designs. Customers can use the powerful floorplanner tool for design optimization and to make regional or site assignments for all block instances. ACE also includes a critical path analysis tool that allows customers to analyze timing. Customers can also use ACE’s powerful Snapshot embedded logic analyzer to create complex triggers and show run-time signals within a Speedcore instance.

About Speedcore Embedded FPGA (eFPGA)

Speedcore embedded FPGA (eFPGA) IP can be integrated into an ASIC or SoC. Customers specify their logic, RAM and DSP resource needs, then Achronix configures the Speedcore IP to meet their individual requirements. Speedcore look-up-tables (LUTs), RAM blocks, DSP64 blocks and custom blocks can be assembled in flexible columns to create the optimal programmable function for any given application.

About Achronix Semiconductor Corporation

Achronix is a privately held, fabless semiconductor corporation based in Santa Clara, California. The Company developed its FPGA technology which is the basis of the Speedster22i FPGAs and Speedcore eFPGA technology. All Achronix FPGA products are supported by its ACE design tools that include integrated support for Synopsys (NASDAQ:SNPS) Synplify Pro. The company has sales offices and representatives in the United States, Europe, and China, and has a research and design office in Bangalore, India.

Leave a Reply

featured blogs
Sep 21, 2023
Wireless communication in workplace wearables protects and boosts the occupational safety and productivity of industrial workers and front-line teams....
Sep 21, 2023
Labforge is a Waterloo, Ontario-based company that designs, builds, and manufactures smart cameras used in industrial automation and defense applications. By bringing artificial intelligence (AI) into their vision systems with Cadence , they can automate tasks that are diffic...
Sep 21, 2023
At Qualcomm AI Research, we are working on applications of generative modelling to embodied AI and robotics, in order to enable more capabilities in robotics....
Sep 21, 2023
Not knowing all the stuff I don't know didn't come easy. I've had to read a lot of books to get where I am....
Sep 21, 2023
See how we're accelerating the multi-die system chip design flow with partner Samsung Foundry, making it easier to meet PPA and time-to-market goals.The post Samsung Foundry and Synopsys Accelerate Multi-Die System Design appeared first on Chip Design....

Featured Video

Chiplet Architecture Accelerates Delivery of Industry-Leading Intel® FPGA Features and Capabilities

Sponsored by Intel

With each generation, packing millions of transistors onto shrinking dies gets more challenging. But we are continuing to change the game with advanced, targeted FPGAs for your needs. In this video, you’ll discover how Intel®’s chiplet-based approach to FPGAs delivers the latest capabilities faster than ever. Find out how we deliver on the promise of Moore’s law and push the boundaries with future innovations such as pathfinding options for chip-to-chip optical communication, exploring new ways to deliver better AI, and adopting UCIe standards in our next-generation FPGAs.

To learn more about chiplet architecture in Intel FPGA devices visit https://intel.ly/45B65Ij

featured paper

Intel's Chiplet Leadership Delivers Industry-Leading Capabilities at an Accelerated Pace

Sponsored by Intel

We're proud of our long history of rapid innovation in #FPGA development. With the help of Intel's Embedded Multi-Die Interconnect Bridge (EMIB), we’ve been able to advance our FPGAs at breakneck speed. In this blog, Intel’s Deepali Trehan charts the incredible history of our chiplet technology advancement from 2011 to today, and the many advantages of Intel's programmable logic devices, including the flexibility to combine a variety of IP from different process nodes and foundries, quicker time-to-market for new technologies and the ability to build higher-capacity semiconductors

To learn more about chiplet architecture in Intel FPGA devices visit: https://intel.ly/47JKL5h

featured chalk talk

Industry 4.0: From Conception to Value Generation
Industry 4.0 has brought a lot of exciting innovation to the manufacturing and industrial factories throughout the world, but getting your next IIoT design from concept to reality can be a challenging process. In this episode of Chalk Talk, Adithya Madanahalli from Würth Elektronik and Amelia Dalton explore how Würth Elektronik can help you jump start your next IIoT design.
Apr 17, 2023
19,991 views