Big companies have divisions. Big EDA companies have synthesis divisions and design-for-test (DFT) divisions.
Clearly the two have nothing to do with each other. They’re different technologies applied at different times in the flow.
So why in the heck would Oasys, a synthesis company (not big enough yet for divisions) announce DFT support? Sounds like a classic distraction, trying to do too much.
Actually, that’s not how they see it. In fact, since most DFT hardware can be described in RTL, you can presumably do a better job by … Read More → "Is That Any of Your Business?"
Roughly a year ago we talked about Vennsa’s OnPoint tool for identifying what went wrong during verification when something goes wrong. I got an update at DAC recently, where they talked about two concepts they’ve brought to their technology in order to make it easier to decide what to fix when there’s a problem.
The first is that of triage, which automatically tries to combine different failures if they appear to have the same root cause. Prior to this, … Read More → "Sorting Through the Rubble"
Digital designers have had semi-automated design flows for a long time; custom and analog designers, not so much.
Pulsic recently announced that they’re taking some of the custom EDA technology they’ve had for ten years, combining it with new technology, and integrating it into a flow as their Pulsic Planning Solution. I got a chance to talk to them about it at DAC.
Their solution consists of four components:
Last-minute chip design changes are always unfortunate, whether right before cutting masks or, worse yet, after you get silicon back. Some major tool environments provide engineering change order (ECO) support, some don’t. But it’s always a less-than-perfect scenario: an ideal top-down flow would maintain the chain of refinement from the most abstract representation down to the final details. Making a change only at the low level breaks that.
But the practical fact is that, if you’ve spent weeks and months getting things just the way you want them – with the … Read More → "Chip Design Tweaker"
A couple months back we looked at Mentor’s approach to testing 3D ICs. Cadence and Imec have recently announced an automated solution for testing 3D ICs. Their methodology accounts for various stages of assembly and test, including pre-bond, mid-bond, post-bond, and post-packaging, providing “test wrappers” for each of these. Insertion of these wrappers into the chip design is claimed to take less than 0.2% additional die area.
More info in their release…
… Read More → "Another Way to Test Your 3D ICs"IP can be a pain in the butt. Any large company will presumably have tons of IP, some from inside, some from outside, being used in a variety of projects. Each piece of IP may be changed to do things differently or even to fix bugs. If two or more projects rely on the same IP, then those changes might benefit all the projects, or they might diverge. Regardless, it can be really, really hard to manage all of this across a large company.
IC Manage recently did a Read More → "New Tools for Managing IP"
Not long ago we looked at how EDA is shaping up in the cloud, including work that Synopsys has been doing to make VCS available for bursty relief usage. I was fortunate enough to attend a demo session to show how what has heretofore been an interesting theoretical discussion could be made concrete.
Synopsys spent a lot of effort on cloud computing at DAC this year, including a cloud partners booth. Various names, both obvious and some not so, were in the booth: Amazon, … Read More → "An Almost-Cloudy San Diego Day"
Back in May, we talked about Veridae taking their erstwhile all-things-for-all-designers debug product Clarus and cut its coverage to SoCs only, introducing a new Corus product for FPGAs. And for single FPGAs, to be specific. This left uncovered the other area that the original Clarus was going to cover: multiple FPGAs.
That final piece is now in place, as Certus. So, to summarize, we have:
While complementary e-beam lithography (CEBL) provides a new twist on how EBL can be worked into high-volume manufacturing, there are a couple other companies actively pursuing EBL technology.
KLA-Tencor has a technology they refer to as REBL: reflective electron beam lithography. Funded as a DARPA project, it amasses a whopping 106 beams. Interestingly, the payoff is throughput that’s 100x faster than what a single-beam can do, giving a decidedly sub-linear throughput boost. They’re seeing up to 10 wafers/hour for via and contact … Read More → "Other EBL Guys"
