High-level synthesis (HLS) has been all about C (or C++) to RTL. But when you’re validating your algorithm, it’s easier to work at the TLM level for thorough simulations that can complete in your lifetime. But once you’re done with that and ready to create gates, you need more than a TLM model; you need a detailed pin-level model, and so far that’s been a manual job.

Mentor is trying to make this easier by separating out the interface portion of the module, and then allowing for either TLM … Read More → "Switching Classes"

When two chips talk to each other, they do so over a convoluted path that involves signals leaving a driver, going to a pad, up through a wire and other package interconnect, up and down and around along a board trace, and back into and through a package to another pad, finally arriving at the desired input. All along the way they brush up against other signals that may also be switching very quickly. Meanwhile, the power driving the output and input circuits may experience noise (and, in fact, that noise may be different on each chip). When you& … Read More → "End-to-End Signal Analysis"

When you need to verify test suites that drag on for millions (or billions) of clock cycles, it really helps to run them on some hardware – assuming you need clock accuracy. Otherwise, well, “legacy code” acquires a new meaning: the project you started and passed to your progeny because simulation couldn’t finish in your lifetime.

There are various emulation systems out there, but if you’ve done a lot of work on your own prototype, then redoing the design on an emulator might seem like redundant work.

In the … Read More → "Home-Brewed Emulators"

When Imec and Atrenta recently announced a design flow for planning and routing signals between different stacked ICs, I thought, “Wait, I’ve seen this before, with a different name.” I wrote about Javelin’s role in this process a couple years ago. And it occurred to me that Javelin had been pretty quiet, and maybe I’d missed an acquisition or something.

So I checked the website – at first glance, everything seems in order. Then I … Read More → "A New 3D IC Manager"

A couple years ago, in an article about clock-generated noise, we talked about Teklatech’s power-shaping feature, which, at the time, was designed to smooth out the noise spectrum by making as few clock edges coincident as possible. Well, they’ve just released a new version that provides more control over the spectrum: you can design in what you want.

In conjunction with new multi-mode, multi-corner (MMMC) support, you can actually optimize different modes for different spectra concurrently by focusing in on the key noisy … Read More → "Allocating Spectrum"

As flexible as FPGAs are, you would think that you could stuff debug logic in there to probe around the internals and figure out what’s going on when you’ve got a problem.

And, if you’ve been paying attention, you’d say, “Yeah, Altera’s SignalTap and Xilinx’s ChipScope have been doing that for years.”

Well, Springsoft has just announced a ProbeLink product that sounds remarkably similar. What’s different?

The primary low-level differences are the following:

–  & … Read More → "Take it Outside"