A couple months back we looked at Mentor’s approach to testing 3D ICs. Cadence and Imec have recently announced an automated solution for testing 3D ICs. Their methodology accounts for various stages of assembly and test, including pre-bond, mid-bond, post-bond, and post-packaging, providing “test wrappers” for each of these. Insertion of these wrappers into the chip design is claimed to take less than 0.2% additional die area.
More info in their release…
 Intel's Chiplet Leadership Delivers Industry-Leading Capabilities at an Accelerated PaceSponsored by Intel We're proud of our long history of rapid innovation in #FPGA development. With the help of Intel's Embedded Multi-Die Interconnect Bridge (EMIB), we’ve been able to advance our FPGAs at breakneck speed. In this blog, Intel’s Deepali Trehan charts the incredible history of our chiplet technology advancement from 2011 to today, and the many advantages of Intel's programmable logic devices, including the flexibility to combine a variety of IP from different process nodes and foundries, quicker time-to-market for new technologies and the ability to build higher-capacity semiconductors To learn more about chiplet architecture in Intel FPGA devices visit: https://intel.ly/47JKL5h |
