A couple months back we looked at Mentor’s approach to testing 3D ICs. Cadence and Imec have recently announced an automated solution for testing 3D ICs. Their methodology accounts for various stages of assembly and test, including pre-bond, mid-bond, post-bond, and post-packaging, providing “test wrappers” for each of these. Insertion of these wrappers into the chip design is claimed to take less than 0.2% additional die area.
More info in their release…
 How Google and Intel use Calibre DesignEnhancer to reduce IR drop and improve reliabilitySponsored by Siemens Digital Industries Software Through real-world examples from Intel and Google, we highlight how Calibre’s DesignEnhancer maximizes layout modifications while ensuring DRC compliance. |
