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Another Way to Test Your 3D ICs

A couple months back we looked at Mentor’s approach to testing 3D ICs. Cadence and Imec have recently announced an automated solution for testing 3D ICs. Their methodology accounts for various stages of assembly and test, including pre-bond, mid-bond, post-bond, and post-packaging, providing “test wrappers” for each of these. Insertion of these wrappers into the chip design is claimed to take less than 0.2% additional die area.

More info in their release

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Speeding Up Large-Scale EM Simulation of ICs Without Compromising Accuracy

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With growing on-chip RF content, electromagnetic (EM) simulation of passives is critical — from selecting the right RF design candidates to detecting parasitic coupling. Being on-chip, accurate EM analysis requires a tie in to the process technology with process design kits (PDKs) and foundry-certified EM simulation technology. Anything short of that could compromise the RFIC’s functionality. Learn how to get the highest-in-class accuracy and 10X faster analysis.

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