editor's blog
Subscribe Now

Veridae Drops the Third Shoe

Back in May, we talked about Veridae taking their erstwhile all-things-for-all-designers debug product Clarus and cut its coverage to SoCs only, introducing a new Corus product for FPGAs. And for single FPGAs, to be specific. This left uncovered the other area that the original Clarus was going to cover: multiple FPGAs.

That final piece is now in place, as Certus. So, to summarize, we have:

  • Clarus for SoCs
  • Corus for single FPGAs
  • Certus for multiple FPGAs

They also announced that they’ve worked with the Dini group to provide a development and debug platform supporting up to 20 FPGAs or 130 million ASIC gates; and they’ve been worked into Mentor’s FPGA design flow.

Their releases have more information on Certus, the Dini arrangement, and the Mentor flow

Leave a Reply

featured blogs
Jun 17, 2019
One topic that garnered much interest at the Samtec booth at the International Microwave Symposium was a dynamic stress test of Samtec’s microwave cable. This demonstration proves that our low-loss, microwave cable withstands high flex cycles and still maintains signal ...
Jun 17, 2019
You know what it's like, right? Those sudden urges to declutter the house. Well, during one such exercise, my niece stumbled across some cassettes and looked at them like they were from some... [[ Click on the title to access the full blog on the Cadence Community site....
Jun 14, 2019
By Flint Yoder – Mentor, A Siemens Business Tight schedules? Worried about product reliability? Now you can find and eliminate latch-up sensitivity during schematic design, and avoid those post-layout nightmares. Latch-up'€¦the bane of circuit designers and circuit ve...
Jan 25, 2019
Let'€™s face it: We'€™re addicted to SRAM. It'€™s big, it'€™s power-hungry, but it'€™s fast. And no matter how much we complain about it, we still use it. Because we don'€™t have anything better in the mainstream yet. We'€™ve looked at attempts to improve conven...