Back in May, we talked about Veridae taking their erstwhile all-things-for-all-designers debug product Clarus and cut its coverage to SoCs only, introducing a new Corus product for FPGAs. And for single FPGAs, to be specific. This left uncovered the other area that the original Clarus was going to cover: multiple FPGAs.

That final piece is now in place, as Certus. So, to summarize, we have:

• Clarus for SoCs
• Corus for single FPGAs
• Certus for multiple FPGAs

They also announced that they’ve worked with the Dini group to provide a development and debug platform supporting up to 20 FPGAs or 130 million ASIC gates; and they’ve been worked into Mentor’s FPGA design flow.

Their releases have more information on Certus, the Dini arrangement, and the Mentor flow…