editor's blog
Subscribe Now

Sorting Through the Rubble

Roughly a year ago we talked about Vennsa’s OnPoint tool for identifying what went wrong during verification when something goes wrong. I got an update at DAC recently, where they talked about two concepts they’ve brought to their technology in order to make it easier to decide what to fix when there’s a problem.

The first is that of triage, which automatically tries to combine different failures if they appear to have the same root cause. Prior to this, you would manually ask the tool for possible root causes for each failure; now this evaluation and “binning” (more or less) occurs automatically.

The thing is, any given failure may have more than one candidate root cause, and there may be several failures, some of whose candidate root causes overlap. Understanding this picture and the conclusions the tool draws from it falls into the second new concept, which they call causality analysis. This involves a more precise understanding of all root cause candidates and the trajectories of the possible fixes – that is, the knock-on implications of each fix.

In particular, where a given fix candidate is a candidate for several failures, that fix will get a higher ranking than if it only solves a single failure.

In evaluating which fixes to suggest and how to rank them, it also takes into account the complete set of facts regarding which checkers may have blessed or frowned on various parts of the simulation; any available information regarding the desired state of the system at the failed point; whether a given fix would break something else; and whether it would be better to apply a fix further upstream or downstream in the logic.

One key goal of the improvements is to make it easier to figure out who owns a fix. If a set of failures gets grouped during triage, it’s more evident that there’s an owner for the entire group.

More info in their release

Leave a Reply

featured blogs
Apr 11, 2021
https://youtu.be/D29rGqkkf80 Made in "Hawaii" (camera Ziyue Zhang) Monday: Dynamic Duo 2: The Sequel Tuesday: Gall's Law and Big Ball of Mud Wednesday: Benedict Evans on Tech in 2021... [[ Click on the title to access the full blog on the Cadence Community sit...
Apr 8, 2021
We all know the widespread havoc that Covid-19 wreaked in 2020. While the electronics industry in general, and connectors in particular, took an initial hit, the industry rebounded in the second half of 2020 and is rolling into 2021. Travel came to an almost stand-still in 20...
Apr 7, 2021
We explore how EDA tools enable hyper-convergent IC designs, supporting the PPA and yield targets required by advanced 3DICs and SoCs used in AI and HPC. The post Why Hyper-Convergent Chip Designs Call for a New Approach to Circuit Simulation appeared first on From Silicon T...
Apr 5, 2021
Back in November 2019, just a few short months before we all began an enforced… The post Collaboration and innovation thrive on diversity appeared first on Design with Calibre....

featured video

Meeting Cloud Data Bandwidth Requirements with HPC IP

Sponsored by Synopsys

As people continue to work remotely, demands on cloud data centers have never been higher. Chip designers for high-performance computing (HPC) SoCs are looking to new and innovative IP to meet their bandwidth, capacity, and security needs.

Click here for more information

featured paper

Understanding Functional Safety FIT Base Failure Rate Estimates per IEC 62380 and SN 29500

Sponsored by Texas Instruments

Functional safety standards such as IEC 61508 and ISO 26262 require semiconductor device manufacturers to address both systematic and random hardware failures. Base failure rates (BFR) quantify the intrinsic reliability of the semiconductor component while operating under normal environmental conditions. Download our white paper which focuses on two widely accepted techniques to estimate the BFR for semiconductor components; estimates per IEC Technical Report 62380 and SN 29500 respectively.

Click here to download the whitepaper

featured chalk talk

TDK Magnetic Sheets For EMI and NFC Applications

Sponsored by Mouser Electronics and TDK

Today’s dense, complex designs can be extremely challenging from an EMI perspective. Re-designs of PCBs to eliminate problems can be expensive and time consuming, and a manufacturing solution can be preferable. In this episode of Chalk Talk, Amelia Dalton chats with Chris Burket of TDX about Flexield noise suppression sheets, which may be just what your design needs to get EMI under control.

Click here for more information about TDK Flexield Noise Suppression Sheets