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Safe Processing

When we recently looked at software and hardware safety standards, much of the discussion was focused on process-oriented standards like DO-254 and DO-178. But we also mentioned some other standards without going into detail. And some of those operate on the concept of “safety integrity level,” or SIL.

The origin of this concept is IEC 61508, which establishes four SILs, numbered 1-4, with 4 indicating the “safest” level. The determination of SIL appears to be … Read More → "Safe Processing"

A new way to do metal

I noticed an interesting release courtesy of Leti, the French research consortium. It concerns a new way of depositing metal that looks so easy that it clearly must not be (or else everyone would have been doing it).

Copper has become the standard metal for logic processes. It uses a series of standard photolithographic steps to deposit, pattern, and etch the metal. The problem is that the cost of this process has been prohibitive for other smaller non-logic chips whose price can’t support such a process.

A French company, Replisaurus, has developed a … Read More → "A new way to do metal"

Keep it in Software

In the domain of deciding which embedded functionality should go in hardware and which in software, some architects have a philosophy of keeping as much in software as possible. That’s because software is inherently much more flexible than hardware. Even if you’re using an FPGA, there’s always the, “what if it doesn’t route?” fear. With software, as long as it fits in the allocated code store, you can do anything you want.

This is, of course, part of the motivation of software-define radio (SDR). Years ago, I … Read More → "Keep it in Software"

A New Spin on Logic

Way back in 2008, we took a look at MRAM technology. As a brief review, you may recall that Crocus in particular takes advantage of tunneling magneto-resistance between two magnetic layers. The bottom layer is fixed, or “pinned” and acts as a reference layer. The top one – also referred to as the “free” or “storage” layer – can have its magnetic polarity (or, more accurately, moment) reversed. Selectivity can be improved by engineering the materials so that a current during the write operation will heat the cell and lower the “coercivity” … Read More → "A New Spin on Logic"

Starting from Scratch

In this “advanced” age of EDA, it’s not uncommon for new point tools to come along, improving some bottleneck in an otherwise reasonably well-established tool chain. What’s less common is for an entire new tool flow to emerge. And it’s even less common yet for one to emerge all from a single company. And a small one, no less.

And yet that’s what’s happened recently in the analog/custom world. Vivid Engineering, at its roots a design services house, has launched Symica (they haven’ … Read More → "Starting from Scratch"

Is That Any of Your Business?

Big companies have divisions. Big EDA companies have synthesis divisions and design-for-test (DFT) divisions.

Clearly the two have nothing to do with each other. They’re different technologies applied at different times in the flow.

So why in the heck would Oasys, a synthesis company (not big enough yet for divisions) announce DFT support? Sounds like a classic distraction, trying to do too much.

Actually, that’s not how they see it. In fact, since most DFT hardware can be described in RTL, you can presumably do a better job by … Read More → "Is That Any of Your Business?"

Sorting Through the Rubble

Roughly a year ago we talked about Vennsa’s OnPoint tool for identifying what went wrong during verification when something goes wrong. I got an update at DAC recently, where they talked about two concepts they’ve brought to their technology in order to make it easier to decide what to fix when there’s a problem.

The first is that of triage, which automatically tries to combine different failures if they appear to have the same root cause. Prior to this, … Read More → "Sorting Through the Rubble"

Another Way to Test Your 3D ICs

A couple months back we looked at Mentor’s approach to testing 3D ICs. Cadence and Imec have recently announced an automated solution for testing 3D ICs. Their methodology accounts for various stages of assembly and test, including pre-bond, mid-bond, post-bond, and post-packaging, providing “test wrappers” for each of these. Insertion of these wrappers into the chip design is claimed to take less than 0.2% additional die area.

More info in their release

Read More → "Another Way to Test Your 3D ICs"

New Tools for Managing IP

IP can be a pain in the butt. Any large company will presumably have tons of IP, some from inside, some from outside, being used in a variety of projects. Each piece of IP may be changed to do things differently or even to fix bugs. If two or more projects rely on the same IP, then those changes might benefit all the projects, or they might diverge. Regardless, it can be really, really hard to manage all of this across a large company.

IC Manage recently did a Read More → "New Tools for Managing IP"

An Almost-Cloudy San Diego Day

Not long ago we looked at how EDA is shaping up in the cloud, including work that Synopsys has been doing to make VCS available for bursty relief usage. I was fortunate enough to attend a demo session to show how what has heretofore been an interesting theoretical discussion could be made concrete.

Synopsys spent a lot of effort on cloud computing at DAC this year, including a cloud partners booth. Various names, both obvious and some not so, were in the booth: Amazon, … Read More → "An Almost-Cloudy San Diego Day"

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