editor's blog
Subscribe Now

A new way to do metal

I noticed an interesting release courtesy of Leti, the French research consortium. It concerns a new way of depositing metal that looks so easy that it clearly must not be (or else everyone would have been doing it).

Copper has become the standard metal for logic processes. It uses a series of standard photolithographic steps to deposit, pattern, and etch the metal. The problem is that the cost of this process has been prohibitive for other smaller non-logic chips whose price can’t support such a process.

A French company, Replisaurus, has developed a completely different way of depositing metal, and it requires no photolithography at all. Instead, a template is formed for the metal pattern. The template consists of a mask-like wafer within which the metal pattern has been etched to form trenches.

When used, these trenches are filled with metal, so the patterning for the entire wafer is already in place. A seed layer is deposited on the silicon wafer, and then the template is placed on the wafer. The template and the wafer act as electrodes, and the metal in the template is “sucked” onto the wafer, depositing the entire pattern in one go.

A bit of etching gets rid of the unwanted portions of the seed layer, and you’re good to go.

This saves a lot of processing steps as well as avoiding the issues surrounding photolithography. But they also make one more claim that’s a bit surprising (and, so far, my request for clarification has gone unanswered): they say no CMP is needed. It’s hard to imagine the metal going down smoothly on a rough substrate – especially on top of other layers of metal. There must be something I’m missing there…

More info and pointers on Leti’s release

Leave a Reply

featured blogs
Nov 23, 2022
The current challenge in custom/mixed-signal design is to have a fast and silicon-accurate methodology. In this blog series, we are exploring the Custom IC Design Flow and Methodology stages. This methodology directly addresses the primary challenge of predictability in creat...
Nov 22, 2022
Learn how analog and mixed-signal (AMS) verification technology, which we developed as part of DARPA's POSH and ERI programs, emulates analog designs. The post What's Driving the World's First Analog and Mixed-Signal Emulation Technology? appeared first on From Silicon To So...
Nov 21, 2022
By Hossam Sarhan With the growing complexity of system-on-chip designs and technology scaling, multiple power domains are needed to optimize… ...
Nov 18, 2022
This bodacious beauty is better equipped than my car, with 360-degree collision avoidance sensors, party lights, and a backup camera, to name but a few....

featured video

How to Harness the Massive Amounts of Design Data Generated with Every Project

Sponsored by Cadence Design Systems

Long gone are the days where engineers imported text-based reports into spreadsheets and sorted the columns to extract useful information. Introducing the Cadence Joint Enterprise Data and AI (JedAI) platform created from the ground up for EDA data such as waveforms, workflows, RTL netlists, and more. Using Cadence JedAI, engineering teams can visualize the data and trends and implement practical design strategies across the entire SoC design for improved productivity and quality of results.

Learn More

featured paper

How SHP in plastic packaging addresses 3 key space application design challenges

Sponsored by Texas Instruments

TI’s SHP space-qualification level provides higher thermal efficiency, a smaller footprint and increased bandwidth compared to traditional ceramic packaging. The common package and pinout between the industrial- and space-grade versions enable you to get the newest technologies into your space hardware designs as soon as the commercial-grade device is sampling, because all prototyping work on the commercial product translates directly to a drop-in space-qualified SHP product.

Click to read more

featured chalk talk

Beyond the SOT23: The Future of Smaller Packages

Sponsored by Mouser Electronics and Nexperia

There is a megatrend throughout electronic engineering that is pushing us toward smaller and smaller components and printed circuit boards. In this episode of Chalk Talk, Tom Wolf from Nexperia and Amelia Dalton explore the benefits of a smaller package size for the SOT23. They investigate how new package sizes for this SMD can lower your BOM, decrease your board space and more.

Click here for more information about Nexperia SOT23 Surface-Mounted Package Products