editor's blog
Subscribe Now

A new way to do metal

I noticed an interesting release courtesy of Leti, the French research consortium. It concerns a new way of depositing metal that looks so easy that it clearly must not be (or else everyone would have been doing it).

Copper has become the standard metal for logic processes. It uses a series of standard photolithographic steps to deposit, pattern, and etch the metal. The problem is that the cost of this process has been prohibitive for other smaller non-logic chips whose price can’t support such a process.

A French company, Replisaurus, has developed a completely different way of depositing metal, and it requires no photolithography at all. Instead, a template is formed for the metal pattern. The template consists of a mask-like wafer within which the metal pattern has been etched to form trenches.

When used, these trenches are filled with metal, so the patterning for the entire wafer is already in place. A seed layer is deposited on the silicon wafer, and then the template is placed on the wafer. The template and the wafer act as electrodes, and the metal in the template is “sucked” onto the wafer, depositing the entire pattern in one go.

A bit of etching gets rid of the unwanted portions of the seed layer, and you’re good to go.

This saves a lot of processing steps as well as avoiding the issues surrounding photolithography. But they also make one more claim that’s a bit surprising (and, so far, my request for clarification has gone unanswered): they say no CMP is needed. It’s hard to imagine the metal going down smoothly on a rough substrate – especially on top of other layers of metal. There must be something I’m missing there…

More info and pointers on Leti’s release

Leave a Reply

featured blogs
Sep 15, 2019
https://youtu.be/bcAO52jxk10 Made at SFO (camera Carey Guo) Monday: HOT CHIPS: In-DRAM Compute Tuesday: CDNLive India 2019: NXP and More Wednesday: EDPS Preview 2019 Thursday: Intelligent Systems... [[ Click on the title to access the full blog on the Cadence Community site....
Sep 13, 2019
In the video above, Samtec’s Jignesh Shah and Kevin Burt explain that as data rate requirements approach and surpass 112 Gbps PAM4, developers are challenged with balancing increasing throughput, scalability, and density demands with concerns such as power consumption, ...