editor's blog
Subscribe Now

A New Spin on Logic

Way back in 2008, we took a look at MRAM technology. As a brief review, you may recall that Crocus in particular takes advantage of tunneling magneto-resistance between two magnetic layers. The bottom layer is fixed, or “pinned” and acts as a reference layer. The top one – also referred to as the “free” or “storage” layer – can have its magnetic polarity (or, more accurately, moment) reversed. Selectivity can be improved by engineering the materials so that a current during the write operation will heat the cell and lower the “coercivity” of the material – meaning that you switch that storage layer’s cell without disturbing any other cell. Crocus refers to this as thermally-assisted switching.

With that background (and recommending you to the original article for the details), Crocus has announced what they call a “magnetic logic unit” (MLU). They claim this capability lets them implement a NOR memory architecture, a NAND architecture, or an XOR cell.

They’re still being a bit cautious about the details of how this works, but Crocus’s Barry Hoberman took me though the XOR scenario. Before we can go all the way there, we should take one intermediate step by changing how a cell is read.

Originally, we had a pinned reference layer, and we read the cell by measuring the resistance through the cell. Relatively lower resistance means both layers magnetized alike (or in “alignment”); higher resistance meaning they’re magnetized oppositely (or in “anti-alignment”). So the first step we’re going to take is to remove the pinning. Now the reference layer – also called the “sense” layer, since it helps sense the state of the cell – is magnetically “floating”. Then add some metal lines so that you can magnetize the sense layer as north or south. (To pick arbitrary names for two magnetic states).

To read the cell, first set the sense layer to north and do a resistance read; then, very quickly, switch the sense layer to south and do another read. This is a differential-mode read; whichever resistance is higher establishes the polarity of the storage node.

But here’s where the XOR characteristic comes in: you can ignore the specific northness or southness of the fields. If the two layers – sense and storage – have the same polarity (regardless of what it is), they will run lower resistance; if they have opposite polarity, they’ll have higher resistance. That’s the very definition of the exclusive-OR function (assuming low resistance means 1).

Exactly where all of this will lead product-wise isn’t clear yet. They discuss a number of applications of the NAND and XOR capability, but right now it’s just a technology story. Presumably, staying tuned will give us the rest of the story at some point.

More details in Crocus’s release

Leave a Reply

featured blogs
Jan 22, 2021
Amidst an ongoing worldwide pandemic, Samtec continues to connect with our communities. As a digital technology company, we understand the challenges and how uncertain times have been for everyone. In early 2020, Samtec Cares suspended its normal grant cycle and concentrated ...
Jan 22, 2021
I was recently introduced to the concept of a tray that quickly and easily attaches to your car'€™s steering wheel (not while you are driving, of course). What a good idea!...
Jan 22, 2021
This is my second post about this year's CES. The first was Consumer Electronics Show 2021: GM, Intel . AMD The second day of CES opened with Lisa Su, AMD's CEO, presenting. AMD announced new... [[ Click on the title to access the full blog on the Cadence Community...
Jan 20, 2021
Explore how EDA tools & proven IP accelerate the automotive design process and ensure compliance with Automotive Safety Integrity Levels & ISO requirements. The post How EDA Tools and IP Support Automotive Functional Safety Compliance appeared first on From Silicon...

featured paper

Overcoming Signal Integrity Challenges of 112G Connections on PCB

Sponsored by Cadence Design Systems

One big challenge with 112G SerDes is handling signal integrity (SI) issues. By the time the signal winds its way from the transmitter on one chip to packages, across traces on PCBs, through connectors or cables, and arrives at the receiver, the signal is very distorted, making it a challenge to recover the clock and data-bits of the information being transferred. Learn how to handle SI issues and ensure that data is faithfully transmitted with a very low bit error rate (BER).

Click here to download the whitepaper

featured chalk talk

Thunderbolt Technology Overview

Sponsored by Mouser Electronics and Intel

Thunderbolt is the closest thing we’ve got to universal interconnect between a wide variety of devices and systems. With a universal USB-C connector, it can do video, power, data communication - all at scalable rates with smart adjustment. In this episode of Chalk Talk, Amelia Dalton chats with Sandeep Vedanthi of Intel about the latest in Thunderbolt technology - Thunderbolt 4, which brings a number of benefits over previous versions.

Click here for more information about Intel 8000 series Thunderbolt™ 4 Controllers