Jim Turley

Veridae Drops the Third Shoe

June 7, 2011

Back in May, we talked about Veridae taking their erstwhile all-things-for-all-designers debug product Clarus and cut its coverage to SoCs only, introducing a new Corus product for FPGAs. And for single FPGAs, to be specific. This left uncovered the other area that the original Clarus was going to cover: multiple FPGAs.

That final piece is now in place, as Certus. So, to summarize, we have:

Clarus for … Read More → "Veridae Drops the Third Shoe"

Quicker LTE Validation

by Jim Turley

May 23, 2011

Each new communications protocol adds to the complexity of its predecessor, and the 3GPP-LTE cellular standard is no exception. According to Synopsys, there are more than a thousand tests specified in the standard to ensure compliance.

And it’s actually twice that bad: before you cut a chip, you need to verify the design against those tests. Then, when the chip comes out, you need to verify the actual silicon against the same tests.

For this reason, Synopsys – maker of pre-silicon design tools – and Rhode & Schwarz – maker of post-silicon, real, … Read More → "Quicker LTE Validation"

Coming to a Screen Near You?

by Jim Turley

May 17, 2011

Just over a year ago, we took a look at quantum dots, at least in the incarnation that Nanosys was giving them in smaller LCDs. Well, they’ve just announced a new process of applying to the dots to films so that they can be used to form larger screens – arbitrarily large, including TVs. They call the result Quantum Dot Enhancement Film (QDEF).

According to them, your colorful screen isn’t showing you nearly what it could be. By a … Read More → "Coming to a Screen Near You?"

Making Virtual Conferences Cool

by Jim Turley

May 17, 2011

Making Virtual Conferences Cool

Virtual events seem to be all the rage these days. This year, in my industry, a number of long-running events are now “going virtual”. Sponsors, event creators, and attendees are all dizzy with excitement about their transition to the 21st Century. I’ve even “attended” a few myself to see what all the buzz was about.

Now, I’m certainly no luddite. Obviously, since I run a company whose sole purpose is delivering technical content through new mediums, I’m no late adopter, either. I always … Read More →

Joining the Chorus

by Jim Turley

May 16, 2011

We’ve just been through ESC and are heading towards DAC. Both of these are “go-to” events for marketing: lots of announcements, lots of press meetings.

And yet, one of the recommendations you frequently hear as a marketer is that shows are a bad place to announce things. There’s so much going on, there are so many people making announcements, that you get lost in the noise. It’s really hard to stand out; your marketing energy is dissipated in friction, not in results. (Of course, if everybody stopped announcing at … Read More → "Joining the Chorus"

Monopoly as the Efficient Model

by Jim Turley

May 2, 2011

Mentor CEO Wally Rhines gave a keynote presentation at the recent U2U event and, once you connected all the dots in the presentation, he seemed to make a startling suggestion: that industries with monopolies are more efficient than those with many competitors.

Of course, that’s not exactly how he said it. Rather than talking in terms of monopoly versus competition, he worded it as specialization versus generalization, and the point is that specialization is more efficient.

He used Alcoa as an example. At one time, there was no one but Alcoa for … Read More → "Monopoly as the Efficient Model"

Get Wreal

by Jim Turley

May 2, 2011

When analog design discussions turn to simulation, especially when they involve Cadence, one inevitably comes up against the unfortunately-named concept of the “wreal” type. I say “unfortunately” because, pronounced with standard English rules, it’s pronounced “real,” providing no audible distinction from the “real” type. So it’s typically pronounced “double-you-real.” (Or occasionally you’ll hear “w^uh-real.& … Read More → "Get Wreal"

DDR3 System On-and-Around the Chip

by Jim Turley

April 29, 2011

We saw the other day that Cadence was being aggressive with the memory controller IP from their Denali side. They’re actually trying to create a wider-scoped solution by providing a PCB package that ties in well with their DDR3 memory controller IP.

DDR memory timing is simply nuts, and board layout is critical. Everything matters. So the DDR3 Design-in kit contains the memory controller I/O and IC package model, timing/duration model, connector model, memory model, DIMM topology, and electrical constraints for the controller … Read More → "DDR3 System On-and-Around the Chip"

Going Up

by Jim Turley

April 25, 2011

It’s always helpful when complex new technological ideas can be related to everyday concepts. So when I heard about “test elevators,” proposed by imec, for 3D IC DFT, naturally my interest was piqued. It’s an intriguing image, conjuring up thoughts of complex ways of managing tests on multiple dice.

Alas, as it turns out, there’s really no new technology associated with this: it’s simply the idea of allocating some TSVs for testing. Which … Read More → "Going Up"

FLASH Gets Even Smaller

by Jim Turley

April 22, 2011

It feels, at first blush, like the conventional wisdom about floating gate cells not having a future at tiny dimensions may have to go the way lots of conventional wisdom goes. On the heels of Kilopass’s 40-nm MTP announcement, Micron and Intel announced NAND FLASH at as low as 20 nm.

So much for not scalable below 90 nm.

The issue here is too much tunneling when the oxides get too thin. It wasn’t supposed to work with oxides … Read More → "FLASH Gets Even Smaller"