editor's blog
Subscribe Now

Safe Processing

When we recently looked at software and hardware safety standards, much of the discussion was focused on process-oriented standards like DO-254 and DO-178. But we also mentioned some other standards without going into detail. And some of those operate on the concept of “safety integrity level,” or SIL.

The origin of this concept is IEC 61508, which establishes four SILs, numbered 1-4, with 4 indicating the “safest” level. The determination of SIL appears to be relatively complex and somewhat ambiguous since the specific failure modes must be identified for each individual system, and are not codified in IEC 61508. They involve both process considerations as well as the Probability of Failure on Demand, or PFD,  (or its inverse, the Risk Reduction Factor, or RRF).

It’s actually pretty easy to understand the PFD ranges for each SIL: it’s the maximum number of zeros after the decimal for the PFD (or the minimum number of zeros in the RRF). So SIL 1 applies to a PFD of 0.1 to 0.01 (or an RRF of 10 to 100); SIL 4 applies to a PFD of 0.0001-0.00001 (or an RRF of 10,000-100,000).

ISO 26262 has a similar concept for automobiles, referring to Automotive SILs, or ASILs.

Only systems can achieve a SIL level; components may tout a SIL level, but simply using such components (or a process known to have achieved a certain SIL level on a different product) is not sufficient to demonstrate that SIL level. So, for instance, when TI just announced their Hercules microcontrollers, they didn’t say that “these  microcontrollers conform to SIL x.” They listed a series of features that are specifically designed to help a designer achieve a desired SIL or ASIL.

Because these standards don’t call out specific functional requirements, only probabilities of failure and process requirements, the feature list itself can’t be expressly correlated with specifics of the standard. Again, they’re simply things that are known to allow the implementation of safer systems.

More details and the specific features can be found in TI’s release

Leave a Reply

featured blogs
Jul 10, 2020
[From the last episode: We looked at the convolution that defines the CNNs that are so popular for machine vision applications.] This week we'€™re going to do some more math, although, in this case, it won'€™t be as obscure and bizarre as convolution '€“ and yet we will...
Jul 10, 2020
I need a problem that lends itself to being solved using a genetic algorithm; also, one whose evolving results can be displayed on my 12 x 12 ping pong ball array....
Jul 9, 2020
It happens all the time. We'€™re online with a designer and we'€™re looking at a connector in our picture search. He says '€œI need a connector that looks just like this one, but '€¦'€ and then he goes on to explain something he needs that'€™s unique to his desig...

featured video

Product Update: Protect IoT SoCs with DesignWare OTP NVM IP

Sponsored by Synopsys

Join Krishna Balachandran in this discussion on Synopsys DesignWare OTP NVM IP, including security, performance, power, and cost considerations. With more than 12 years of development and deployment by 500+ customers, Synopsys is the leader in antifuse-based OTP NVM IP.

Click here for more information about Synopsys DesignWare OTP NVM IP

Featured Chalk Talk

Hello FPGA

Sponsored by Mouser Electronics and Microchip

Getting started on an FPGA-based embedded vision project can be tricky. Locating all the components you need, getting them to talk to each other, and just getting your system to the video equivalent of “Hello World” is a pretty daunting task. In this episode of Chalk Talk, Amelia Dalton chats with Avery Williams of Microchip Technology about the Hello FPGA kit - a low-cost, low-touch embedded vision kit for engineers new to FPGAs.

More information about Microchip Technology Hello FPGA Kit