fish fry
Subscribe Now

Reality is Not Linear

The Changing Landscape of Physical Design

At what point in the creation of a chip does physical design actually begin? (Spoiler Alert: answers may vary.) In this week’s episode of Fish Fry, Dave Stratman and I discuss the ongoing challenges of the physical design process, why convergent design flows are critical for today’s ever shrinking process nodes, and how form factor and the environment around the end customer affects physical design. We also check out the details of the world’s first 3nm test chip rolled out by Imec and Cadence Design Systems this week.

Download this episode (right click and save)

Links for March 2, 2018

More information about Digital Design and Signoff (Cadence Design Systems)

Imec and Cadence Tape Out Industry’s First 3nm Test Chip

Fish Fry Executive Interviews

Darrin Billerbeck, CEO – Lattice Semiconductor

Anupam Bakshi, CEO – Agnisys

Dave Kleidermacher, CTO – Green Hills Software

Robert Blake, CEO – Achronix

Jack Harding, CEO – eSilicon

Michiel Ligthart, COO – Verific

Adnan Hamid, CEO – Breker Technologies

Jeff Waters, VP and General Manager – Altera

Simon Davidmann, CEO – Imperas

Ted Miracco, CEO – SmartFlow Compliance Solutions

Jessica Gomez – Rogue Valley Microdevices

Shishpal Rawat, Chairman – Accellera Systems Initiative

Kevin Bromber, CEO – myDevices

Daniel Hansson, CEO – Verifyter

Mark Papermaster, CTO – AMD

David Fried, CTO – Coventor

Dr. Steven LeBoeuf, President – Valencell

David Dutton, CEO – Silvaco

Bob Niemiec, CEO – TwistThink

Allan Martinson, COO – Starship Technologies

Zhihong Liu, Chairman and CEO – ProPlus Solutions

Taher Madraswala, CEO and President – Open-Silicon>

Kapil Shankar, CEO and Director – AnDAPT

Dan Fox, CTO – Local Motors

Kim Rowe, Founder and CEO — RoweBots

Lawrence Cooke, Founder and CEO — NovaSolix

Gregg Recupero, CTO — Performance-IP

Alan Grau, CEO — Icon Labs

Carl Alberty, Vice President – Cirrus Logic

Maximilian Odendahl, CEO — Silexica

Finbarr Moynihan, General Manager — MediaTek

Sanjay Pillay, CEO — Austemper

Louis Parks, CEO – SecureRF

Harold Blomquist, CEO – Helix Semiconductor

Dale Dougherty and Sherry Huss, Co-Founders – Maker Faire

Mike Wisart, CEO – efabless

Chris Giovanniello, SVP and Co-Founder – Menlo Micro

Leave a Reply

featured blogs
Jun 22, 2018
A myriad of mechanical and electrical specifications must be considered when selecting the best connector system for your design. An incomplete, first-pass list of considerations include the type of termination, available footprint space, processing and operating temperature...
Jun 22, 2018
You can't finish the board before the schematic, but you want it done pretty much right away, before marketing changes their minds again!...
Jun 22, 2018
Last time I worked for Cadence in the early 2000s, Adriaan Ligtenberg ran methodology services and, in particular, something we called Virtual CAD. The idea of Virtual CAD was to allow companies to outsource their CAD group to Cadence. In effect, we would be the CAD group for...
Jun 7, 2018
If integrating an embedded FPGA (eFPGA) into your ASIC or SoC design strikes you as odd, it shouldn'€™t. ICs have been absorbing almost every component on a circuit board for decades, starting with transistors, resistors, and capacitors '€” then progressing to gates, ALUs...
May 24, 2018
Amazon has apparently had an Echo hiccup of the sort that would give customers bad dreams. It sent a random conversation to a random contact. A couple had installed numerous Alexa-enabled devices in the home. At some point, they had a conversation '€“ as couples are wont to...