Earlier this month, the first rev of the NVM Express (or NVMe) standard was published. The idea is to establish a uniform register and command set for solid-state memories that use PCIe. It’s an abstracted interface, and doesn’t get into such details as wear-leveling; it works at the read/write/erase level, and the memory subsystem itself takes care of implementing low-level algorithms in the appropriate manner.
The architecture defines pairs of transactions – submissions and completions – that are managed on queues configured as circular buffers. There can be multiple submission and … Read More → "PCIe for SSDs"