editor's blog
Subscribe Now

PCIe for SSDs

Earlier this month, the first rev of the NVM Express (or NVMe) standard was published. The idea is to establish a uniform register and command set for solid-state memories that use PCIe. It’s an abstracted interface, and doesn’t get into such details as wear-leveling; it works at the read/write/erase level, and the memory subsystem itself takes care of implementing low-level algorithms in the appropriate manner.

The architecture defines pairs of transactions – submissions and completions – that are managed on queues configured as circular buffers. There can be multiple submission and completion queues; submission queues can be matched with completion queues, or multiple submission queues can share a completion queue. This allows, for example, each core in a multicore system to own a queue without needing locks to protect transactions from interference by other cores.

Quoting from the standard itself, key features are:

  • “Does not require uncacheable / MMIO register reads in the command issue or completion path.
  • A maximum of one MMIO register write is necessary in the command issue path.
  • Support for up to 64K I/O queues, with each I/O queue supporting up to 64K commands.
  • Priority associated with each I/O queue with well-defined arbitration mechanism.
  • All information to complete a 4KB read request is included in the 64B command itself, ensuring
  • efficient small I/O operation.
  • Efficient and streamlined command set.
  • Support for MSI/MSI-X and interrupt aggregation.
  • Support for multiple namespaces.
  • Efficient support for I/O virtualization architectures like SR-IOV.
  • Robust error reporting and management capabilities.”

Key characteristics of the register set are:

  • “Indication of controller capabilities
  • Status for device failures (command status is processed via CQ directly)
  • Admin Queue configuration (I/O Queue configuration processed via Admin commands)
  • Doorbell registers for scalable number of Submission and Completion Queues• Efficient support for I/O virtualization architectures like SR-IOV.
  • Robust error reporting and management capabilities.”

Both Synopsys and Cadence wasted little time in announcing their verification IP support (Cadence also announced 12-Mbps SAS VIP). You can find out more about their announcements in the Synopsys release and the Cadence release, respectively.

Leave a Reply

featured blogs
Jun 13, 2024
I've just been introduced to the DuoFlex 4K Dual-Screen Display from HalmaPixel, and now I'm drooling with desire all over my keyboard....

featured video

Unleashing Limitless AI Possibilities with FPGAs

Sponsored by Intel

Industry experts discuss real-world AI solutions based on Programmable Logic, or FPGAs. The panel talks about a new approach called FPGAi, what it is and how it will revolutionize how innovators design AI applications.

Click here to learn more about Leading the New Era of FPGAi

featured paper

Navigating design challenges: block/chip design-stage verification

Sponsored by Siemens Digital Industries Software

Explore the future of IC design with the Calibre Shift left initiative. In this paper, author David Abercrombie reveals how Siemens is changing the game for block/chip design-stage verification by moving Calibre verification and reliability analysis solutions further left in the design flow, including directly inside your P&R tool cockpit. Discover how you can reduce traditional long-loop verification iterations, saving time, improving accuracy, and dramatically boosting productivity.

Click here to read more

featured chalk talk

GaN FETs: D-Mode Vs E-mode
Sponsored by Mouser Electronics and Nexperia
The use of gallium nitride can offer higher power efficiency, increased power density and can reduce the overall size and weight of many industrial, automotive, and data center applications. In this episode of Chalk Talk, Amelia Dalton and Giuliano Cassataro from Nexperia investigate the benefits of Gan FETs, the difference between D-Mode and E-mode GaN FET technology and how you can utilize GaN FETs in your next design.
Mar 25, 2024
12,356 views