editor's blog
Subscribe Now

PCIe for SSDs

Earlier this month, the first rev of the NVM Express (or NVMe) standard was published. The idea is to establish a uniform register and command set for solid-state memories that use PCIe. It’s an abstracted interface, and doesn’t get into such details as wear-leveling; it works at the read/write/erase level, and the memory subsystem itself takes care of implementing low-level algorithms in the appropriate manner.

The architecture defines pairs of transactions – submissions and completions – that are managed on queues configured as circular buffers. There can be multiple submission and completion queues; submission queues can be matched with completion queues, or multiple submission queues can share a completion queue. This allows, for example, each core in a multicore system to own a queue without needing locks to protect transactions from interference by other cores.

Quoting from the standard itself, key features are:

  • “Does not require uncacheable / MMIO register reads in the command issue or completion path.
  • A maximum of one MMIO register write is necessary in the command issue path.
  • Support for up to 64K I/O queues, with each I/O queue supporting up to 64K commands.
  • Priority associated with each I/O queue with well-defined arbitration mechanism.
  • All information to complete a 4KB read request is included in the 64B command itself, ensuring
  • efficient small I/O operation.
  • Efficient and streamlined command set.
  • Support for MSI/MSI-X and interrupt aggregation.
  • Support for multiple namespaces.
  • Efficient support for I/O virtualization architectures like SR-IOV.
  • Robust error reporting and management capabilities.”

Key characteristics of the register set are:

  • “Indication of controller capabilities
  • Status for device failures (command status is processed via CQ directly)
  • Admin Queue configuration (I/O Queue configuration processed via Admin commands)
  • Doorbell registers for scalable number of Submission and Completion Queues• Efficient support for I/O virtualization architectures like SR-IOV.
  • Robust error reporting and management capabilities.”

Both Synopsys and Cadence wasted little time in announcing their verification IP support (Cadence also announced 12-Mbps SAS VIP). You can find out more about their announcements in the Synopsys release and the Cadence release, respectively.

Leave a Reply

featured blogs
Dec 17, 2018
If row-based placement is a topic that interests you, you might have read our post from the last week . If you haven'€™t read it yet, I'€™d highly recommend it for its focus on the need and benefits of... [[ Click on the title to access the full blog on the Cadence Commu...
Dec 13, 2018
In November, we continued our mobile updates to the website, released a couple of new content experiences, and made placing sample requests even easier. Read more below on these and the rest of the major updates to Samtec.com for November 2018. Continued Improvements to our M...
Dec 12, 2018
The possibilities for IoT devices, much like the internet itself, are endless. But with all of those possibilities comes risks....
Nov 14, 2018
  People of a certain age, who mindfully lived through the early microcomputer revolution during the first half of the 1970s, know about Bill Godbout. He was that guy who sent out crudely photocopied parts catalogs for all kinds of electronic components, sold from a Quon...