editor's blog
Subscribe Now

Graychip Alternatives

Chips that have reached, or are approaching, their end of life have been a perennial problem for systems makers for years. And the solutions have varied over time, with lifetime buys or the selling of the chip design to another company specializing in keeping older technology alive for longer than the original maker is interested in.

I remember seeing an email years ago from a Japanese customer that had decided they needed more of a long-obsolete chip. Their simple request was, “Can you please open up that fab again and make us some more? Kthanxbai.” The expectation was that a customer would never be told, “No,” and that we would re-open the old line, re-install the long-gone process, and make them some more chips. Now… I’m pretty customer-centric, but come on guys… But I digress.

RFEL has announced a new variant on substituting TI’s aging Graychip low-level DSP products: they reproduce the behavior in an FPGA. And there’s some nuance here: it’s actually not correct to say that it’s the behavior they duplicate – it’s the parameters. They may actually use a different algorithm, but they develop it using Matlab, and they use the Matlab models to prove to the customer that the parameters match those of the original Graychip devices.

Of course, this isn’t a pin-for-pin drop-in production replacement; it tends to get worked into a revision when it’s not worth completely re-architecting old functionality that works. It can, however, be a cost reduction.

They support both Altera and Xilinx, although they can’t use the same design for both… of course…

You can find more info in their release

Leave a Reply

featured blogs
Mar 31, 2023
Learn how (and why) the semiconductor industry is moving towards chiplet-enabled multi-die systems in our research piece in MIT's Technology Review Insights. The post An Industry-Wide Look at the Move Toward Multi-Die Systems appeared first on New Horizons for Chip Design....
Mar 31, 2023
The Verisium Debug platform is optimized for scalability, supporting debugging of simulation runs and emulation, where support for loading large source files and handling huge amounts of probe data is a must. Join this free Cadence Training Webinar to learn how to automate yo...
Mar 30, 2023
Are you in desperate need of a program manager to instigate a new project or rescue an existing project that is spiraling out of control?...

featured video

First CXL 2.0 IP Interoperability Demo with Compliance Tests

Sponsored by Synopsys

In this video, Sr. R&D Engineer Rehan Iqbal, will guide you through Synopsys CXL IP passing compliance tests and demonstrating our seamless interoperability with Teladyne LeCroy Z516 Exerciser. This first-of-its-kind interoperability demo is a testament to Synopsys' commitment to delivering reliable IP solutions.

Learn more about Synopsys CXL here

featured chalk talk

Power Multiplexing with Discrete Components
Sponsored by Mouser Electronics and Toshiba
Power multiplexing is a vital design requirement for a variety of different applications today. In this episode of Chalk Talk, Amelia Dalton chats with Talayeh Saderi from Toshiba about what kind of power multiplex solution would be the best fit for your next design. They discuss five unique design considerations that we should think about when it comes to power multiplexing and the benefits that high side gate drivers bring to power multiplexing.
Sep 22, 2022
24,276 views