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And Then There Were Three

Back before the turn of the century, a brash new company called Magma came onto the scene. This was a time when chip design involved a series of complicated tools, each of which required an exporting of the result of one tool and an importing of those results into the next tool. Magma’s claim to fame was the single database, with each tool providing a different view into and operations on that database.

Implicit in such a strategy is a goal of being all things to all customers. No non-Magma point tools would work with … Read More → "And Then There Were Three"

Conditioning Sensor Signals

Some time back, ZMDI made an announcement about a sensor conditioner they had released. A couple things gave me cause for pause as I looked it over. First was the description of a one-pass calibration process as being unique. The other was the fact that a major component of the advanced sensors you may see presented at conferences, examples of which we covered in a sensor article series earlier this year, is the associated circuitry required … Read More → "Conditioning Sensor Signals"

BoardView Becomes SystemNav

Almost two years ago we looked at Magma’s newly-announced BoardView. The idea was to simplify the border crossing between chip and board when tracing signals and tracking down issues.

Magma has now announced the new-and-updated version of this tool, which they’re now calling SystemNav. They’ve essentially increased the reach of the tool to include 3D packages and multi-chip modules as well as chips and boards. But they also say that they’ve fundamentally beefed up the platform to handle more … Read More → "BoardView Becomes SystemNav"

Describing User-Defined Faults

In today’s article on cell-aware fault modeling, we described how specific layout-dependent faults can be accounted for in the test suite, increasing the test coverage beyond what stuck-at modeling provides and yet keeping the vector count down below what gate-exhaustive modeling would require.

But there has to be some way of defining these specific “user-defined” faults so that the test generation program can include them in the test suite.

Mentor devised their so-called “User-Defined Fault Model”, or UDFM, language … Read More → "Describing User-Defined Faults"

A Bit of Memory With Your Logic?

The recent ICCAD show had a session dedicated to MRAM and memristors. Spintec had a presentation on MRAM that went beyond the normal discussion of memory, and proposed a hybrid logic/memory (or logic-in-memory) usage of MRAM cells – or, more precisely, of magnetic tunnel junctions (MTJs).

At the very simplest end of this is a so-called non-volatile flip-flop (NVFF). It normally acts as a standard flip-flop or SRAM cell (with equivalent performance), but on the pull-up end of things are a couple … Read More → "A Bit of Memory With Your Logic?"

What Will the Next Logic Switch Look Like?

The recent edition of ICCAD provided an interesting look at what some of the contenders will be for logic switches once our standard configurations are no longer viable. Just to put things into perspective, FinFETs are old-tech in this timeframe.

 

One of the proposals stopped short of departing silicon: a silicon nano-wire FET. Imagine your standard Montana barbed-wire fence: three strands of wire between two posts. Now imagine that it snowed, and some kids piled up the snow like a wall running between the two fence posts so that the barbed wire strands were … Read More → "What Will the Next Logic Switch Look Like?"

Another Transistor Goes Vertical

While the recent MEMS Executive Congress focused on electro-mechanical applications, occasionally MEMS processing techniques were highlighted for strictly electrical purposes, with no mechanical component.

In one example, ICEMOS talked about their collaboration with MEMS manufacturer Omron for a new way of making superjunction power transistors.

Superjunction transistors overcome the Ron/breakdown tradeoff issue using alternating p and n stripes. In theory, these can be arranged a number of different ways, but, according to ICEMOS, the typical way it’s done now is horizontally, by growing a series of epitaxial layers of … Read More → "Another Transistor Goes Vertical"

A Different TSV

Through-silicon vias (TSVs) are a key technology for stacking chips in so-called 3D (or 2.5D) configurations. And there’s lots of talk about how to use deep reactive ion etching (DRIE) methods to get a nice deep high-aspect-ratio hole and then fill it with metal to make this connection.

But in a conversation with Silex at the MEMS Executive Congress, they pointed out a different approach they take to TSVs. And, it turns out, this approach has been in production for five years, so it’s not exactly new – yet I haven’t … Read More → "A Different TSV"

We Won’t Call You; Just Call Us

One of the challenges with sensors is that, at their most fundamental level, all they do is provide some value reflecting whatever it is they’re sensing. If you want to know that value, you have to go get the value. “You” typically being the main processor in the system.

That’s easy enough if it’s something you occasionally do under the direction of a program, but if you want the sensor to alert you when something happens, then you have to poll constantly so that you know when something changed. … Read More → "We Won’t Call You; Just Call Us"

Getting a Jump on Power Integrity

Apache announced their RTL Power Model (RPM) recently. The idea is that it lets designers understand their power and power integrity issues earlier in the design cycle. “Early,” however, is a relative term. Unlike some technologies that move such estimates to the architectural phase, this moves the capability from post-layout to RTL. That’s not to take anything away from it – they claim it gives designers a six-month jump on the problem.

The way this works involves a number of Apache tools, starting with PowerArtist. Actually, in order for PowerArtist to do its … Read More → "Getting a Jump on Power Integrity"

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