editor's blog
Subscribe Now

A Different TSV

Through-silicon vias (TSVs) are a key technology for stacking chips in so-called 3D (or 2.5D) configurations. And there’s lots of talk about how to use deep reactive ion etching (DRIE) methods to get a nice deep high-aspect-ratio hole and then fill it with metal to make this connection.

But in a conversation with Silex at the MEMS Executive Congress, they pointed out a different approach they take to TSVs. And, it turns out, this approach has been in production for five years, so it’s not exactly new – yet I haven’t seen it discussed in the mainstream (and maybe that’s just me).

What’s different here is that it’s not a metal via: it’s a silicon via. Which gives rise to the clever name SIL-VIA.

It’s predicated on highly-doped bulk silicon. As a pure-play MEMS company, wafers may have characteristics different from that of CMOS wafers. Instead of etching out the entire hole for a pillar of metal, they etch a border around the hole (typically cylindrical, but it can actually be any shape). They then grow oxide in that gap, which now isolates the silicon remaining inside from that outside.

The inside and outside silicon are still connected, since the etch doesn’t go all the way through the wafer. The central core is “released” by grinding away the back. Now the inside portion is isolated, and can form a ½-1-Ω via. This contrasts with the 10-20 mΩ that are more typical of metal vias.

The primary benefit they tout is that the via is thermally matched to the surrounding bulk material, which they say is a problem with metal vias. They also note, of course, that this has been in production for several years; they claim experience on over 50,000 wafers implementing over 100 different products.

There’s a bit more information mid-page on their technology page

Leave a Reply

featured blogs
Sep 21, 2021
Placing component leads accurately as per the datasheet is an important task while creating a package footprint symbol. As the pin pitch goes down, the size and location of the component lead play a... [[ Click on the title to access the full blog on the Cadence Community si...
Sep 21, 2021
Learn how our high-performance FPGA prototyping tools enable RTL debug for chip validation teams, eliminating simulation/emulation during hardware debugging. The post High Debug Productivity Is the FPGA Prototyping Game Changer: Part 1 appeared first on From Silicon To Softw...
Sep 18, 2021
Projects with a steampunk look-and-feel incorporate retro-futuristic technology and aesthetics inspired by 19th-century industrial steam-powered machinery....
Aug 5, 2021
Megh Computing's Video Analytics Solution (VAS) portfolio implements a flexible and scalable video analytics pipeline consisting of the following elements: Video Ingestion Video Transformation Object Detection and Inference Video Analytics Visualization   Because Megh's ...

featured video

Digital Design Technology Symposium

Sponsored by Synopsys

Are you an SoC designer or manager facing new design challenges driven by rapidly growing and emerging vertical segments for HPC, 5G, mobile, automotive and AI applications?

Join us at the Digital Design Technology Symposium.

featured paper

Seamlessly connect your world with 16 new wireless MCUs for the 2.4-GHz and Sub-1-GHz bands

Sponsored by Texas Instruments

Low-power wireless microcontroller (MCU) shipments are expected to double over the next four years to more than 4 billion units. This massive influx of MCUs will result in more opportunities for wireless connectivity than ever before, with growth across a wide range of applications and technologies. With the addition of 16 new wireless connectivity devices, we are empowering you to innovate, scale and accelerate the deployment of wireless connectivity – no matter what or how you are connecting.

Click to read more

featured chalk talk

Time Sensitive Networking for Industrial Automation

Sponsored by Mouser Electronics and Intel

In control applications with strict deterministic requirements, such as those found in automotive and industrial domains, Time Sensitive Networking offers a way to send time-critical traffic over a standard Ethernet infrastructure. This enables the convergence of all traffic classes and multiple applications in one network. In this episode of Chalk Talk, Amelia Dalton chats with Josh Levine of Intel and Patrick Loschmidt of TTTech about standards, specifications, and capabilities of time-sensitive networking (TSN).

Click here for more information about Intel Cyclone® V FPGAs