Through-silicon vias (TSVs) are a key technology for stacking chips in so-called 3D (or 2.5D) configurations. And there’s lots of talk about how to use deep reactive ion etching (DRIE) methods to get a nice deep high-aspect-ratio hole and then fill it with metal to make this connection.
But in a conversation with Silex at the MEMS Executive Congress, they pointed out a different approach they take to TSVs. And, it turns out, this approach has been in production for five years, so it’s not exactly new – yet I haven’t seen it discussed in the mainstream (and maybe that’s just me).
What’s different here is that it’s not a metal via: it’s a silicon via. Which gives rise to the clever name SIL-VIA.
It’s predicated on highly-doped bulk silicon. As a pure-play MEMS company, wafers may have characteristics different from that of CMOS wafers. Instead of etching out the entire hole for a pillar of metal, they etch a border around the hole (typically cylindrical, but it can actually be any shape). They then grow oxide in that gap, which now isolates the silicon remaining inside from that outside.
The inside and outside silicon are still connected, since the etch doesn’t go all the way through the wafer. The central core is “released” by grinding away the back. Now the inside portion is isolated, and can form a ½-1-Ω via. This contrasts with the 10-20 mΩ that are more typical of metal vias.
The primary benefit they tout is that the via is thermally matched to the surrounding bulk material, which they say is a problem with metal vias. They also note, of course, that this has been in production for several years; they claim experience on over 50,000 wafers implementing over 100 different products.
There’s a bit more information mid-page on their technology page…