editor's blog
Subscribe Now

A Different TSV

Through-silicon vias (TSVs) are a key technology for stacking chips in so-called 3D (or 2.5D) configurations. And there’s lots of talk about how to use deep reactive ion etching (DRIE) methods to get a nice deep high-aspect-ratio hole and then fill it with metal to make this connection.

But in a conversation with Silex at the MEMS Executive Congress, they pointed out a different approach they take to TSVs. And, it turns out, this approach has been in production for five years, so it’s not exactly new – yet I haven’t seen it discussed in the mainstream (and maybe that’s just me).

What’s different here is that it’s not a metal via: it’s a silicon via. Which gives rise to the clever name SIL-VIA.

It’s predicated on highly-doped bulk silicon. As a pure-play MEMS company, wafers may have characteristics different from that of CMOS wafers. Instead of etching out the entire hole for a pillar of metal, they etch a border around the hole (typically cylindrical, but it can actually be any shape). They then grow oxide in that gap, which now isolates the silicon remaining inside from that outside.

The inside and outside silicon are still connected, since the etch doesn’t go all the way through the wafer. The central core is “released” by grinding away the back. Now the inside portion is isolated, and can form a ½-1-Ω via. This contrasts with the 10-20 mΩ that are more typical of metal vias.

The primary benefit they tout is that the via is thermally matched to the surrounding bulk material, which they say is a problem with metal vias. They also note, of course, that this has been in production for several years; they claim experience on over 50,000 wafers implementing over 100 different products.

There’s a bit more information mid-page on their technology page

Leave a Reply

featured blogs
Jul 3, 2020
[From the last episode: We looked at CNNs for vision as well as other neural networks for other applications.] We'€™re going to take a quick detour into math today. For those of you that have done advanced math, this may be a review, or it might even seem to be talking down...
Jul 2, 2020
Using the bitwise operators in general -- and employing them to perform masking, bit testing, and bit setting/clearing operations in particular -- can be extremely efficacious....
Jul 2, 2020
In June, we continued to upgrade several key pieces of content across the website, including more interactive product explorers on several pages and a homepage refresh. We also made a significant update to our product pages which allows logged-in users to see customer-specifi...

Featured Video

Product Update: New DesignWare® IOs

Sponsored by Synopsys

Join Faisal Goriawalla for an update on Synopsys’ DesignWare GPIO and Specialty IO IP, including LVDS, I2C and I3C. The IO portfolio is silicon-proven across a range of foundries and process nodes, and is ready for your next SoC design.

Click here for more information about DesignWare Embedded Memories, Logic Libraries and Test Videos

Featured Paper

Cryptography: Fundamentals on the Modern Approach

Sponsored by Maxim Integrated

Learn about the fundamental concepts behind modern cryptography, including how symmetric and asymmetric keys work to achieve confidentiality, identification and authentication, integrity, and non-repudiation.

Click here to download the whitepaper

Featured Chalk Talk

Smart Home Design

Sponsored by Mouser Electronics and NXP

Today’s smart home technologies have to balance scalability in performance, low power, heat dissipation, encoding and decoding standards, and much more. In this episode of Chalk Talk, Amelia Dalton chats with Mark Ruthenbeck of NXP about the nuts and bolts of smart home technology, with a virtual tour of the ultimate smart home.

Click here for more information about NXP Semiconductors i.MX 8M Mini Applications Processors