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ESD on High-Frequency RF Circuits

In our recent piece on board-level ESD protection, I noted that, while the board is protected during actual usage, chip-level ESD protection is focused more on what might happen to the chip during handling, before it’s inserted into its final board resting place.

Such chip-level ESD circuits are mostly standard, typically involving some kind of diode breakdown to shunt excess energy. But this is apparently a dicier deal with RF circuits, since plain vanilla ESD circuits can degrade the RF performance.</ … Read More → "ESD on High-Frequency RF Circuits"

Virtual Platforms for a Non-FPGA

Xilinx has a new challenge on their hands. It’s called “software.” And at ARM TechCon, they announced their software enablement initiative for Zynq.

Of course, this is the same challenge any SoC project has. And SoC designers have a variety of tools to help with this, from virtual platforms to emulators. These allow software development to get up and running before the actual silicon is available.

What’s new is that Xilinx has their spiffy new Zynq family featuring the ARM Cortex A9 MPcore – one or more copies. And … Read More → "Virtual Platforms for a Non-FPGA"

Piezo… what?

The piezoelectric effect is pretty straightforward. With certain crystals, if you apply strain, the separation of dipoles in the crystal will set up a piezopotential.

Let’s take that one step further by making contacts on either end of a nanowire made of an appropriate material – in particular, ZnO, but potentially other so-called “wurtzite” semiconductors. Put a potential across is and use mechanical stress in the nanowire to modulate the current: you’ve basically got a FET, with the nanowire acting as a mechanical gate.

Those contacts are Schottky contacts, … Read More → "Piezo… what?"

Calling all Conspirators!

I wrote a feature article on conspiracy theories among engineers.

What if, instead of “paranoid,” those engineers are really just “perceptive”?  Conspiracies like these folks are suspecting would obviously require a large number of excellent engineers to perpetrate.  No meaningful black helicopter operation could ever get off the ground without some good solid engineering behind it.

So, how about it conspiracy engineers… are you out there?  Are you retired? Have you left the fold?  Talk to us!

How does … Read More → "Calling all Conspirators!"

Fighting Fire with Fire?

Microscopy doesn’t get much attention in the general tech press (although we’re used to seeing really cool pictures taken by scanning electron microscopes (SEMs), whether they’re FinFET cross-sections or nematodes up close).

But in a wafer production line, you need inspection to identify, for example, whether a mask has a defect that could cause yield loss. You can see such defects using different light wavelengths, but the folks at Lawrence Berkeley have remarked that the wavelength makes a big difference in … Read More → "Fighting Fire with Fire?"

ARM’s Top Three Cellular Trends

At ARM’s recent TechCon event, I heard from James Bruce, their lead mobile strategist, who gave his views on the three trends he sees underway on the mobile front.

The first is the continued evolution of the smartphone; no surprise there. These are the machines that are expected to replace your laptop someday. At around $600, they’ll focus on features and performance. (And, addressing my kvetch comment following Jim’s article at the end of that link, yes, evidently docking stations are being … Read More → "ARM’s Top Three Cellular Trends"

Another PCB Tool Refresh

Our feature this week talks about Zuken’s PCB tool redesign, and out of left field came another announcement of yet another PCB tool that has had a major facelift: Intercept’s Pantheon 7.

Much of what they describe as being new in the tool conforms to much of what you would expect from a modern interface (not to minimize the amount of work to bring a new GUI to fruition – and, harder yet, test it on all platforms).

So naturally I wondered whether … Read More → "Another PCB Tool Refresh"

Not All Logic Stages Need to Be Equal

I had a conversation with Cadence at ARM TechCon, and one of the things they’re talking about is what they call clock/data co-optimization as an alternative to traditional synchronous logic optimization.

Typically, designers work hard to make sure each logic stage in the overall logic pipeline can be implemented in the time required before the next clock arrives. Some stages have more logic than others, and you have to spend more time on those ones to get the speed right.

Meanwhile, someone spends a lot of effort synthesizing a clock tree that& … Read More → "Not All Logic Stages Need to Be Equal"

A New Conference Fee Coming Your Way?

Go to any conference, and everything is sponsored. Lunch is sponsored. The coffee is sponsored. The Wifi is sponsored. The salad fork is sponsored (and the sponsor gets upset if you don’t know which one is the salad fork). Like banks, conference producers have found increasing ways of getting companies to offset the cost of doing business while giving them visibility in exchange. (OK, banks don’t give anything in exchange, they just take more money when they want it, so that’s probably an uncharitable comparison. Sorry guys….)

But today I … Read More → "A New Conference Fee Coming Your Way?"

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