editor's blog
Subscribe Now

Describing User-Defined Faults

In today’s article on cell-aware fault modeling, we described how specific layout-dependent faults can be accounted for in the test suite, increasing the test coverage beyond what stuck-at modeling provides and yet keeping the vector count down below what gate-exhaustive modeling would require.

But there has to be some way of defining these specific “user-defined” faults so that the test generation program can include them in the test suite.

Mentor devised their so-called “User-Defined Fault Model”, or UDFM, language to handle this. It’s a human-readable and -writable format, and you can use it to define both static and transition faults. This allows you to describe specific custom faults manually if you wish, although, as described in the article, it would be written out automatically by the tools.

As an example, the following would define the four possible alternative tests for the static fault caused by the low-resistance bridge example in the article:

Fault “Bridge-R4” {

       Test {StaticFault “Z”=0; Condition “S0”=0,”S1”=0,”D0”=0,”D1”=-,”D2”=1}

       Test {StaticFault “Z”=0; Condition “S0”=1,”S1”=0,”D0”=-,”D1”=0,”D2”=1}

       Test {StaticFault “Z”=0; Condition “S0”=0,”S1”=1,”D0”=1,”D1”=-,”D2”=0}

       Test {StaticFault “Z”=0; Condition “S0”=1,”S1”=1,”D0”=-,”D1”=1,”D2”=0}


Leave a Reply

featured blogs
Apr 18, 2021
https://youtu.be/afv9_fRCrq8 Made at Target Oakridge (camera Ziyue Zhang) Monday: "Targeting" the Open Compute Project Tuesday: NUMECA, Computational Fluid Dynamics...and the America's... [[ Click on the title to access the full blog on the Cadence Community s...
Apr 16, 2021
Spring is in the air and summer is just around the corner. It is time to get out the Old Farmers Almanac and check on the planting schedule as you plan out your garden.  If you are unfamiliar with a Farmers Almanac, it is a publication containing weather forecasts, plantin...
Apr 15, 2021
Explore the history of FPGA prototyping in the SoC design/verification process and learn about HAPS-100, a new prototyping system for complex AI & HPC SoCs. The post Scaling FPGA-Based Prototyping to Meet Verification Demands of Complex SoCs appeared first on From Silic...
Apr 14, 2021
By Simon Favre If you're not using critical area analysis and design for manufacturing to… The post DFM: Still a really good thing to do! appeared first on Design with Calibre....

featured video

The Verification World We Know is About to be Revolutionized

Sponsored by Cadence Design Systems

Designs and software are growing in complexity. With verification, you need the right tool at the right time. Cadence® Palladium® Z2 emulation and Protium™ X2 prototyping dynamic duo address challenges of advanced applications from mobile to consumer and hyperscale computing. With a seamlessly integrated flow, unified debug, common interfaces, and testbench content across the systems, the dynamic duo offers rapid design migration and testing from emulation to prototyping. See them in action.

Click here for more information

featured paper

Understanding Functional Safety FIT Base Failure Rate Estimates per IEC 62380 and SN 29500

Sponsored by Texas Instruments

Functional safety standards such as IEC 61508 and ISO 26262 require semiconductor device manufacturers to address both systematic and random hardware failures. Base failure rates (BFR) quantify the intrinsic reliability of the semiconductor component while operating under normal environmental conditions. Download our white paper which focuses on two widely accepted techniques to estimate the BFR for semiconductor components; estimates per IEC Technical Report 62380 and SN 29500 respectively.

Click here to download the whitepaper

featured chalk talk

TI Robotics System Learning Kit

Sponsored by Mouser Electronics and Texas Instruments

Robotics projects can get complicated quickly, and finding a set of components, controllers, networking, and software that plays nicely together is a real headache. In this episode of Chalk Talk, Amelia Dalton chats with Mark Easley of Texas Instruments about the TI-RSLK Robotics Kit, which will get you up and running on your next robotics project in no time.

Click here for more information about the Texas Instruments TIRSLK-EVM Robotics System Lab Kit