editor's blog
Subscribe Now

Describing User-Defined Faults

In today’s article on cell-aware fault modeling, we described how specific layout-dependent faults can be accounted for in the test suite, increasing the test coverage beyond what stuck-at modeling provides and yet keeping the vector count down below what gate-exhaustive modeling would require.

But there has to be some way of defining these specific “user-defined” faults so that the test generation program can include them in the test suite.

Mentor devised their so-called “User-Defined Fault Model”, or UDFM, language to handle this. It’s a human-readable and -writable format, and you can use it to define both static and transition faults. This allows you to describe specific custom faults manually if you wish, although, as described in the article, it would be written out automatically by the tools.

As an example, the following would define the four possible alternative tests for the static fault caused by the low-resistance bridge example in the article:

Fault “Bridge-R4” {

       Test {StaticFault “Z”=0; Condition “S0”=0,”S1”=0,”D0”=0,”D1”=-,”D2”=1}

       Test {StaticFault “Z”=0; Condition “S0”=1,”S1”=0,”D0”=-,”D1”=0,”D2”=1}

       Test {StaticFault “Z”=0; Condition “S0”=0,”S1”=1,”D0”=1,”D1”=-,”D2”=0}

       Test {StaticFault “Z”=0; Condition “S0”=1,”S1”=1,”D0”=-,”D1”=1,”D2”=0}

}

Leave a Reply

featured blogs
Jul 3, 2020
[From the last episode: We looked at CNNs for vision as well as other neural networks for other applications.] We'€™re going to take a quick detour into math today. For those of you that have done advanced math, this may be a review, or it might even seem to be talking down...
Jul 2, 2020
Using the bitwise operators in general, and employing them to perform masking operations in particular, can be extremely efficacious....
Jul 2, 2020
In June, we continued to upgrade several key pieces of content across the website, including more interactive product explorers on several pages and a homepage refresh. We also made a significant update to our product pages which allows logged-in users to see customer-specifi...

Featured Video

Product Update: Advances in DesignWare Die-to-Die PHY IP

Sponsored by Synopsys

Hear the latest about Synopsys' DesignWare Die-to-Die PHY IP for SerDes-based 112G USR/XSR and parallel-based HBI interfaces. The IP, available in advanced FinFET processes, addresses the power, bandwidth, and latency requirements of high-performance computing SoCs targeting hyperscale data center, AI, and networking applications.

Click here for more information about DesignWare Die-to-Die PHY IP Solutions

Featured Paper

Cryptography: How It Helps in Our Digital World

Sponsored by Maxim Integrated

Gain a basic understanding of how cryptography works and how cryptography can help you protect your designs from security threats.

Click here to download the whitepaper

Featured Chalk Talk

Embedded Display Applications Innovation

Sponsored by Mouser Electronics and Texas Instruments

DLP technology can add a whole new dimension to your embedded design. If you considered DLP in the past, but were put off by the cost, you need to watch this episode of Chalk Talk where Amelia Dalton chats with Philippe Dollo of Texas Instruments about the DLP LightCrafter 2000 EVM. This new kit makes DLP more accessible and less expensive to design in, and could have a dramatic impact on your next embedded design.

Click here for more information about Texas Instruments DLP2000 Digital Micromirror Device (DMD)