editor's blog
Subscribe Now

Describing User-Defined Faults

In today’s article on cell-aware fault modeling, we described how specific layout-dependent faults can be accounted for in the test suite, increasing the test coverage beyond what stuck-at modeling provides and yet keeping the vector count down below what gate-exhaustive modeling would require.

But there has to be some way of defining these specific “user-defined” faults so that the test generation program can include them in the test suite.

Mentor devised their so-called “User-Defined Fault Model”, or UDFM, language to handle this. It’s a human-readable and -writable format, and you can use it to define both static and transition faults. This allows you to describe specific custom faults manually if you wish, although, as described in the article, it would be written out automatically by the tools.

As an example, the following would define the four possible alternative tests for the static fault caused by the low-resistance bridge example in the article:

Fault “Bridge-R4” {

       Test {StaticFault “Z”=0; Condition “S0”=0,”S1”=0,”D0”=0,”D1”=-,”D2”=1}

       Test {StaticFault “Z”=0; Condition “S0”=1,”S1”=0,”D0”=-,”D1”=0,”D2”=1}

       Test {StaticFault “Z”=0; Condition “S0”=0,”S1”=1,”D0”=1,”D1”=-,”D2”=0}

       Test {StaticFault “Z”=0; Condition “S0”=1,”S1”=1,”D0”=-,”D1”=1,”D2”=0}

}

Leave a Reply

featured blogs
Jan 19, 2021
As promised, we'€™re back with some more of the big improvements that are part of the QIR2 update release of 17.4 (HotFix 013). This time, everything is specific to our Allegro ® Package Designer... [[ Click on the title to access the full blog on the Cadence Communit...
Jan 19, 2021
I'€™ve been reading year-end and upcoming year lists about the future trends affecting technology and electronics. Topics run the gamut from expanding technologies like 5G, AI, electric vehicles, and various realities (XR, VR, MR), to external pressures like increased gover...
Jan 18, 2021
The DIY electronics portion AliExpress website can be a time-sink for the unwary because one tempting project leads to another....
Jan 14, 2021
Learn how electronic design automation (EDA) tools & silicon-proven IP enable today's most influential smart tech, including ADAS, 5G, IoT, and Cloud services. The post 5 Key Innovations that Are Making Everything Smarter appeared first on From Silicon To Software....

featured paper

Overcoming Signal Integrity Challenges of 112G Connections on PCB

Sponsored by Cadence Design Systems

One big challenge with 112G SerDes is handling signal integrity (SI) issues. By the time the signal winds its way from the transmitter on one chip to packages, across traces on PCBs, through connectors or cables, and arrives at the receiver, the signal is very distorted, making it a challenge to recover the clock and data-bits of the information being transferred. Learn how to handle SI issues and ensure that data is faithfully transmitted with a very low bit error rate (BER).

Click here to download the whitepaper

Featured Chalk Talk

Introducing Google Coral

Sponsored by Mouser Electronics and Google

AI inference at the edge is exploding right now. Numerous designs that can’t use cloud processing for AI tasks need high-performance, low-power AI acceleration right in their embedded designs. Wouldn’t it be cool if those designs could have their own little Google TPU? In this episode of Chalk Talk, Amelia Dalton chats with James McKurkin of Google about the Google Coral edge TPU.

More information about Coral System on Module