editor's blog
Subscribe Now

Getting a Jump on Power Integrity

Apache announced their RTL Power Model (RPM) recently. The idea is that it lets designers understand their power and power integrity issues earlier in the design cycle. “Early,” however, is a relative term. Unlike some technologies that move such estimates to the architectural phase, this moves the capability from post-layout to RTL. That’s not to take anything away from it – they claim it gives designers a six-month jump on the problem.

The way this works involves a number of Apache tools, starting with PowerArtist. Actually, in order for PowerArtist to do its thing, one other piece has to be in place: a so-called PACE model.

A PACE model provides an estimate of a cell’s parasitics for a given technology. It’s done once, along with the development of the cell, and the PACE model becomes part of the designer’s kit.

That PACE model, along with other technology information, then feeds PowerArtist, which looks through the RTL and infers cells for the circuit. Even though no layout has been done, by knowing the cells, you can call up the PACE model and estimate the parasitics and power implications.

You then simulate your design, and PowerArtist creates the RPM. It does this by calculating an estimate of the energy consumed by each cell as it runs and dividing that by the clock period to derive a power-per-cycle metric for each cell. Those are summed together, and, from that, the tool can identify both power peaks and events with rapid current changes (high di/dt).

For each of these types of event, they define a “frame” around it – roughly 10 or so clock cycles, which includes both the lead-up to and follow-up from the event. The RPM consists of these frames, accompanied by various libraries and pieces of proprietary information that can then be delivered to the RedHawk tool.

With this information, RedHawk will build a current waveform for each clock cycle in each frame. With that waveform, you can use RedHawk to play with early power grid ideas or to start working on chip/package co-design issues, focusing only on those events known to be a challenge.

So this lets you get started dealing with potential power integrity issues long before the layout is available to give you exact results. Obviously, the analysis will need to be repeated for confirmation when the layout is ready, but, hopefully, by then, the major issues will already have been addressed.

More info in their release

Leave a Reply

featured blogs
Feb 22, 2024
The new Cadence training website is online! This newly redesigned website provides an overview of our well-respected training methods and courses, plus offerings that might be new to you. Modern design and top-of-the-page navigation make it easy to find just what you need'”q...
Feb 15, 2024
This artist can paint not just with both hands, but also with both feet, and all at the same time!...

featured video

Shape The Future Now with Synopsys ARC-V Processor IP

Sponsored by Synopsys

Synopsys ARC-V™ Processor IP delivers the optimal power-performance-efficiency and extensibility of ARC processors with broad software and tools support from Synopsys and the expanding RISC-V ecosystem. Built on the success of multiple generations of ARC processor IP covering a broad range of processor implementations, including functional safety (FS) versions, the ARC-V portfolio delivers what you need to optimize and differentiate your SoC.

Learn more about Synopsys ARC-V RISC-V Processor IP

featured paper

Reduce 3D IC design complexity with early package assembly verification

Sponsored by Siemens Digital Industries Software

Uncover the unique challenges, along with the latest Calibre verification solutions, for 3D IC design in this new technical paper. As 2.5D and 3D ICs redefine the possibilities of semiconductor design, discover how Siemens is leading the way in verifying complex multi-dimensional systems, while shifting verification left to do so earlier in the design process.

Click here to read more

featured chalk talk

Data Connectivity at Phoenix Contact
Single pair ethernet provides a host of benefits that can enable seamless data communication for a variety of different applications. In this episode of Chalk Talk, Amelia Dalton and Guadalupe Chalas from Phoenix Contact explore the role that data connectivity will play for the future of an all electric society, the benefits that single pair ethernet brings to IIoT designs and how Phoenix Contact is furthering innovation in this arena.
Jan 5, 2024
7,628 views