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Getting a Jump on Power Integrity

Apache announced their RTL Power Model (RPM) recently. The idea is that it lets designers understand their power and power integrity issues earlier in the design cycle. “Early,” however, is a relative term. Unlike some technologies that move such estimates to the architectural phase, this moves the capability from post-layout to RTL. That’s not to take anything away from it – they claim it gives designers a six-month jump on the problem.

The way this works involves a number of Apache tools, starting with PowerArtist. Actually, in order for PowerArtist to do its thing, one other piece has to be in place: a so-called PACE model.

A PACE model provides an estimate of a cell’s parasitics for a given technology. It’s done once, along with the development of the cell, and the PACE model becomes part of the designer’s kit.

That PACE model, along with other technology information, then feeds PowerArtist, which looks through the RTL and infers cells for the circuit. Even though no layout has been done, by knowing the cells, you can call up the PACE model and estimate the parasitics and power implications.

You then simulate your design, and PowerArtist creates the RPM. It does this by calculating an estimate of the energy consumed by each cell as it runs and dividing that by the clock period to derive a power-per-cycle metric for each cell. Those are summed together, and, from that, the tool can identify both power peaks and events with rapid current changes (high di/dt).

For each of these types of event, they define a “frame” around it – roughly 10 or so clock cycles, which includes both the lead-up to and follow-up from the event. The RPM consists of these frames, accompanied by various libraries and pieces of proprietary information that can then be delivered to the RedHawk tool.

With this information, RedHawk will build a current waveform for each clock cycle in each frame. With that waveform, you can use RedHawk to play with early power grid ideas or to start working on chip/package co-design issues, focusing only on those events known to be a challenge.

So this lets you get started dealing with potential power integrity issues long before the layout is available to give you exact results. Obviously, the analysis will need to be repeated for confirmation when the layout is ready, but, hopefully, by then, the major issues will already have been addressed.

More info in their release

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