The recent ICCAD show had a session dedicated to MRAM and memristors. Spintec had a presentation on MRAM that went beyond the normal discussion of memory, and proposed a hybrid logic/memory (or logic-in-memory) usage of MRAM cells – or, more precisely, of magnetic tunnel junctions (MTJs).
At the very simplest end of this is a so-called non-volatile flip-flop (NVFF). It normally acts as a standard flip-flop or SRAM cell (with equivalent performance), but on the pull-up end of things are a couple of MTJs oppositely biased. Those can act as a permanently stored state: when an “auto-zero” function is performed using an additional transistor, the FF stops acting like a FF and acts like a sense amp instead. The unbalancing of what is essentially a diff pair biases the circuit in one direction so that, in a few hundred picoseconds, you can restore the stored state. Add a couple transistors needed to provide the heating current for thermally-assisted switching of the MTJs, and you have a way to dynamically change the non-volatile state.
This can help, for example, when powering down a block to save power. Before doing so, if you save the value in the MTJ pair, then the block can save its state and come back up with no loss of memory. Another example of this concept is a non-volatile L2 cache that can be powered-down and restored with no loss.
The Laboratoire d’Informatique, de Robotique et de Microélectronique de Montpellier (LIRMM) has gone so far as to put together an FPGA where the flip-flops and SRAM cells have been replaced by MTJs. Now, after capturing the FPGA content via a serial stream and storing it in the MTJs, you can have sub-1-ns configuration after power-up from then on – no serial loading.
The logic-in-memory concept embeds MTJs into standard logic circuits. They showed an adder example where two added transistors act as a latch above a current-mode adder. There’s an MTJ in each leg of the adder above the current source. The current source itself is dynamic, being clocked to reduce power.
This all works because the MTJ can be built above the logic rather than next to the logic, as is typical for CMOS or other memory. This allows more seamless mixing of MTJs and logic, and it reduces the distance between logic and computation, improving performance and increasing the opportunities for interconnectivity. The MTJ can be programmed quickly (on the order of 10 ns vs a 2-ns write time for a volatile SRAM bit).
In the adder example, area and performance improved nominally using the hybrid approach, but dynamic power went from over 70 µW to just over 16 µW; standby power went from 0.9 nW to 0 nW (since the current source can be shut off). The only metric that went in the wrong direction was the amount of energy needed to write the cell: it went from 4 pJ in the pure CMOS implementation to almost 7 pJ for the hybrid version – and just over 20 pJ for writing the MTJ.
