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DVCon and the Big Data Problem

Design and verification technologies are front and center in this week’s episode of Fish Fry. DVCon General Chair Dennis Brophy joins us with a special sneak peak of the 2018 Design and Verification Conference. Dennis and I chat about how the biggest trends are reflected at DVCON, including machine learning, automotive technologies, and big data analysis. We also discuss the addition of shorter format workshops to … Read More → "DVCon and the Big Data Problem"

Plunify – The Big FPGA Guns

Eyes scan the optimization options like a master pool player about to run the table against a hapless opponent. Solids and stripes form a map – a complex mathematical model where LUTs and connections melt away and a unique strategy emerges. Quick optimization to get the lay of the land, 7 ball in the side pocket, multiple runs for timing, park the cue ball left to set up for the 5 in … Read More → "Plunify – The Big FPGA Guns"

Climbing the PowerTree™

From source to sink to the current in-between, this week’s Fish Fry is all about power delivery and how we can solve our power delivery network problems. My guest is Brad Griffin (Cadence Design Systems) and we’re talking about how we can catch the PDN issues earlier in our design cycles and how “shifting left” can make all the difference in your next PCB design. Keeping with … Read More → "Climbing the PowerTree™"

Heavy Lifting

In this week’s episode of Fish Fry, we tackle lifecycle traceability and standard compliance in the world of safety and security electronic design. Jim McElroy (LDRA) and I chat about about why test management can be especially helpful when designing for the functional safety and secure market, and how newly introduced automation in the LDRA tool suite can your software compliance ducks in a row faster than ever … Read More → "Heavy Lifting"

Altium Amps PCB

Altium (long ago known as Protel) has long distinguished themselves as the provider of PCB tools for the mainstream. They based their business on the notion that many designers and small design teams don’t have the budget, patience, or need for the big enterprise-scale board design tools offered by EDA companies like Mentor and Cadence. Instead, they focused on the “desktop” market, blazing … Read More → "Altium Amps PCB"

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featured blogs
Feb 23, 2018
The IEEE-SA has a policy of keeping standards active by making sure they get a cycle of updates every 10 years. Including Verilog, SystemVerilog has been going on a cycle of updates every 5±1 years since 1995. I wrote here about the updates to 1800-2009 and 1800-2012, and no...
Feb 23, 2018
What is a software GPS, what does it have to do with Tensilica DSP IP, and why would anyone care? To answer that, let's start with a quiz from the transportation industry. How many shipping containers are currently in transit around the world? It turns out that no one kn...
Feb 22, 2018
We’ve spent a good chunk of the last year building a new on-site search experience for Samtec.com. This update continues that trend with our newly released competitor cross reference search addition. Using this feature, you can access competitor cross reference data for...
Jan 19, 2018
Artificial intelligence (AI) is reshaping the way the world works, opening up countless opportunities in commercial and industrial systems. Applications span diverse markets such as autonomous driving, medical diagnostics, home appliances, industrial automation, adaptive webs...
chalk talks
Moving Between FPGA and ASIC with High-Level Synthesis Writing RTL that works smoothly on both FPGA and ASIC implementations is nearly impossible. But, High-Level Synthesis (HLS) can make technology-independent design a breeze. In this episode of Chalk Talk, Amelia Dalton chats with Stuart Clubb of Mentor’s Catapult team about how to use HLS to accelerate your design flow. Click here for more … Read More → "Moving Between FPGA and ASIC with High-Level Synthesis"
Scaling Embedded Deep Learning Inference Performance with Dedicated Neural Network DSP   Neural networks are taking over a broad range of exciting applications these days. But, the amount of computation required for neural network inferencing can be daunting. In this episode of Chalk Talk, Amelia Dalton chats with Pulin Desai of Cadence Design Systems about some new processor IP designed specifically for neural network inferencing. … Read More → "Scaling Embedded Deep Learning Inference Performance with Dedicated Neural Network DSP"
IDesignSpec: Executable Register SpecificationGetting RTL right for your chip design is a difficult engineering and verification challenge with very high stakes. And, most of us use a variety of tools – including spreadsheets and text documents – to capture our design intent and details. In this episode of Chalk Talk, Amelia Dalton chats with Anupam Bakshi from Agnisys … Read More → "IDesignSpec: Executable Register Specification"
Protium S1, the Most Productive FPGA-Based Prototyping SolutionFPGA-based prototypes are essential in most system designs today. But, building your own prototype is a challenging and expensive proposition. You need a robust solution with performance, scalability, software support, visibility, and a host of other important attributes. In this episode of Chalk Talk, Amelia Dalton chats with Juergen Jaeger about the Protium S1 FPGA-based … Read More → "Protium S1, the Most Productive FPGA-Based Prototyping Solution"
Cadence Xcelium Parallel Simulator: Third Generation Parallel VerificationGetting the best RTL simulation performance is a combination of improving single-core speed and cleverly partitioning the task so that parallel machines can give you the kind of performance boost you’d expect. In this episode of Chalk Talk, Amelia Dalton chats with Dave Lidrbauch from Cadence Design Systems about Xcelium – Cadence’s third-generation parallel RTL simulation … Read More → "Cadence Xcelium Parallel Simulator: Third Generation Parallel Verification"
Pegasus Verification System: Let Your DRC Fly!Design rule checking (DRC) can be the one of the biggest bottlenecks in getting a chip out the door. The computation power required for a large DRC run can be staggering. In this episode of Chalk Talk, Amelia Dalton chats with Christen Decoin from Cadence Design Systems about the Pegasus Verification System which will let your … Read More → "Pegasus Verification System: Let Your DRC Fly!"