EDA
Subscribe to EE Journal Daily Newsletter

The Next Frontier of Functional Verification

This week’s episode of Fish Fry runs the gamut of electronic design. First, check out how an Italian engineering student built a 3D printer for only twelve dollars! (Spoiler alert: He used recycled parts from three inkjet printers and a flatbed scanner). Next, Breker CEO Adnan Hamid joins us to discuss the controversy around portable stimulus representation models, the future of portable stimulus, and why … Read More → "The Next Frontier of Functional Verification"

Clocks, Xs, and Resets

Does it ever feel to you like, no matter how many new tools features appear, it’s never quite enough? In some cases, you solve one problem – but it doesn’t stay solved. Complexity, scaling, performance and power requirements – they may all catch up to the solution, necessitating further tool refinement. In other cases, new problems arise that were never dealt with before.

< … Read More → "Clocks, Xs, and Resets"

Why Are Design Tools So Bad?

As much as the EDA industry would like us to believe otherwise, it’s almost impossible to find an engineering team who is satisfied with their design tools. More often than not, when chatting with designers about their tools, we get sentiments ranging from “survivable” to “horrible.” The “survivable” end of the spectrum usually amounts to something on the order of, “We managed to get the … Read More → "Why Are Design Tools So Bad?"

Plumbing for High Performance Computing

In this week’s episode of Fish Fry, data center technology rules the roost. We can toil away at the world’s greatest IoT design, embedded computer, or specialized IC – but it’s the diligence of datacenter technology that holds the key to the success of our electronic design community. In this week’s Fish Fry, we take a closer look at two different aspects of data … Read More → "Plumbing for High Performance Computing"

System Delta Sigma Delta

System Design is inherently a task of integration. The job of the system engineer is to gather and integrate a collection of components which, taken together, will solve some problem, while meeting a list of requirements such as form factor, performance, functionality, power consumption, reliability, and cost.

Almost all of the components we choose will be sourced from third parties. Seldom (if ever) these days is there … Read More → "System Delta Sigma Delta"

EDA Tackles Functional Safety

For years, when we have thought “functional safety” or “safety-critical design,” we’ve pictured airplanes, spaceships, and weapons. All of these systems rely on tons of electronics, and they have to work properly or else bad things happen – either lots of time and money lost or lives lost.

And so, for years, the “mil/aero” world has been its own … Read More → "EDA Tackles Functional Safety"

September 19, 2017
September 18, 2017
September 15, 2017
September 14, 2017
September 13, 2017
September 12, 2017
September 11, 2017
September 7, 2017
September 6, 2017
September 5, 2017
August 23, 2017
August 10, 2017
August 9, 2017
August 7, 2017
July 27, 2017
July 26, 2017
featured blogs
Sep 18, 2017
A friend of mine was saying the other day, “I want to be able to go to my car, type something like New York City , take a nap, and have the car wake me when I get there.” My friend lives in California; barring supersonic auto 2 [*] transportation, it would be a long...
Sep 15, 2017
Glass Weave Skew. For most people it probably sounds like a progressive rock band. But we’re talking about Glass Weave Skew and differential signals. Brandon Gore, Senior Staff Signal Integrity Engineer, and the Manager of Samtec’s Signal Integrity Group, R&D...
Sep 01, 2017
Achronix was delighted to attend the Hot Chips event in Cupertino once again this August. This year saw a bumper turnout, with some very fascinating speakers providing some great insights into the industry. The Achronix team had a chance to meet with many talented people in t...
chalk talks
Cadence Xcelium Parallel Simulator: Third Generation Parallel VerificationGetting the best RTL simulation performance is a combination of improving single-core speed and cleverly partitioning the task so that parallel machines can give you the kind of performance boost you’d expect. In this episode of Chalk Talk, Amelia Dalton chats with Dave Lidrbauch from Cadence Design Systems about Xcelium – Cadence’s third-generation parallel RTL simulation … Read More → "Cadence Xcelium Parallel Simulator: Third Generation Parallel Verification"
Pegasus Verification System: Let Your DRC Fly!Design rule checking (DRC) can be the one of the biggest bottlenecks in getting a chip out the door. The computation power required for a large DRC run can be staggering. In this episode of Chalk Talk, Amelia Dalton chats with Christian Decoin from Cadence Design Systems about the Pegasus Verification System which will let your … Read More → "Pegasus Verification System: Let Your DRC Fly!"
JasperGold RTL Designer Signoff with Superlint and CDCRTL signoff is becoming the preferred design methodology for many teams today. But, verifying that your RTL will give you back the chip you want – the first time – is a challenging task. In this episode of Chalk Talk, Amelia Dalton chats with Pete Hardee of Cadence Design Systems about JasperGold, a comprehensive solution … Read More → "JasperGold RTL Designer Signoff with Superlint and CDC"
Tanner Designer: Analog VerificationMost design teams struggle with verification on the analog portion of their designs. While huge strides have been made in digital design over the past decade, analog design remains  more of a mystery for many engineers. In this episode of Chalk Talk, Amelia Dalton chats with Mass Sivilotti from Mentor about Tanner Designer – a … Read More → "Tanner Designer: Analog Verification"
Fixed Point, Floating Point – What Are the Needs of DSP Applications?When implementing DSP algorithms, the tradeoff between fixed- and floating-point math can have huge implications on performance and precision. In this episode of Chalk Talk, Amelia Dalton chats with Pushkar Patwardhan of Cadence Design Systems about making the critical decisions on floating-point versus fixed-point. Click here for more information about Tensilica Customizable Processor and DSP IP.
IoT and The Power of PSpiceToday's IoT designs demand some complex mixed-mode, mixed-signal simulation to be sure that they'll work correctly across wide ranges of component variation, temperature, and other real-world conditions. In this episode of Chalk Talk, Amelia Dalton chats with John Carney of Cadence Design Systems about PSpice mixed-signal simulation for IoT.