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Tower of Power

Power is the name of the game in this week’s episode of Amelia’s Weekly Fish Fry. We’re talking about all things power-related; from “Shift Left” power signoff to the super cool capabilities of near threshold voltage computing. Kenneth Chang (Synopsys) joins us to discuss why power integrity and reliability can make or break chip design and how RedHawk Analysis … Read More → "Tower of Power"

Where’s the CNN Synthesis?

The electronic design automation (EDA’s) mission has always been primarily to facilitate the design and verification of electronic circuits. EDA began, of course, with companies like Mentor, Daisy, and Valid providing specialized software for capturing and editing schematic drawings. These tools took the native human-readable language of the designer: schematics, and created the fundamental machine-readable structure of EDA: the netlist.

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Virtual Verification Smorgasbord

Pull up a chair. Take a taste. Come join us. Life is so endlessly delicious. — Ruth Reichl

Are you ready for a virtual buffet of verification goodness? I hope so. In this week’s Fish Fry, we’re gobbling down as much verification as we possibly can fit on our podcastin’ plate. First up, Anupam Bakshi (Agnisys) joins us to dish on register specification, automatic … Read More → "Virtual Verification Smorgasbord"

Sigrity Elevates 3D

Signal integrity (SI) is the bane of most system designers. Getting those signals to pass intact through all the twists and turns of your design can be a maddening experience. But modern signal integrity design and analysis is the enabling soul of most of today’s high-performance systems. Cadence’s Sigrity tools are an industry leader in the signal and power integrity game, and the recently … Read More → "Sigrity Elevates 3D"

Intel Acquires eASIC – Why?

Intel announced last week that they are acquiring structured ASIC company eASIC into their Programmable Systems Group (PSG). If you haven’t been following along in your major merger primer, Intel PSG was formerly known as Altera – one of the two major players in the FPGA market. Altera has played second fiddle to Xilinx in the Duopoly Symphony for the past twenty seasons or so. This … Read More → "Intel Acquires eASIC – Why?"

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featured blogs
Aug 18, 2018
Once upon a time, the Santa Clara Valley was called the Valley of Heart'€™s Delight; the main industry was growing prunes; and there were orchards filled with apricot and cherry trees all over the place. Then in 1955, a future Nobel Prize winner named William Shockley moved...
Aug 17, 2018
Samtec’s growing portfolio of high-performance Silicon-to-Silicon'„¢ Applications Solutions answer the design challenges of routing 56 Gbps signals through a system. However, finding the ideal solution in a single-click probably is an obstacle. Samtec last updated the...
Aug 17, 2018
If you read my post Who Put the Silicon in Silicon Valley? then you know my conclusion: Let's go with Shockley. He invented the transistor, came here, hired a bunch of young PhDs, and sent them out (by accident, not design) to create the companies, that created the compa...
Aug 16, 2018
All of the little details were squared up when the check-plots came out for "final" review. Those same preliminary files were shared with the fab and assembly units and, of course, the vendors have c...
Jul 30, 2018
As discussed in part 1 of this blog post, each instance of an Achronix Speedcore eFPGA in your ASIC or SoC design must be configured after the system powers up because Speedcore eFPGAs employ nonvolatile SRAM technology to store its configuration bits. The time required to pr...
chalk talks
Scaling Up Vision and AI DSP Performance  For high-performance, low-power processing of AI and machine vision algorithms, latency can be critical. In this episode of Chalk Talk, Amelia Dalton chats with Pulin Desai from Cadence Design Systems about the using the new Vision Q6 processor core for embedded vision and AI applications. Click here for more information about Vision DSPs for … Read More → "Scaling Up Vision and AI DSP Performance"
Debug and Verify FPGA Algorithms with MATLAB and Simulink   Today’s FPGA designs require industrial-strength functional verification. The ad-hoc methods that worked with older, smaller FPGAs just don’t cut it anymore. In this episode of Chalk Talk, Amelia Dalton chats with Eric Cigan of MathWorks about ASIC-strength functional verification with model-based design. Click here for more information about how to verify VHDL and … Read More → "Debug and Verify FPGA Algorithms with MATLAB and Simulink"
Simulation-Based Tuning of Power Electronics Controllers   Power electronics are becoming more complex these days, and simulating your digital power controller gives significant advantages. In this episode of Chalk Talk, Amelia Dalton chats with Arkadiy Turevskiy of MathWorks about how to tune digital power electronics controllers with simulation. Click here for more information about Simulation-Based Tuning of Power Electronics Controllers.
Addressing Challenges with Large SerDes System Designs  The latest high-speed SerDes standards put high demands on PCB design. In this episode of Chalk Talk, Amelia Dalton chats with Cristian Filip of Mentor about best practices and tools you can apply to implementing and validating the SerDes design on your next circuit board. Click here for more information about SerDes Channel Design … Read More → "Addressing Challenges with Large SerDes System Designs"
Via to Via Coupling Through Plane Cavities   Via to via crosstalk can be a challenging issue in PCB design, and there are a number of myths and misconceptions about how to best reduce it. In this episode of Chalk Talk, Amelia Dalton chats with Fadi Deek from Mentor about the physics behind via to via crosstalk and how to best … Read More → "Via to Via Coupling Through Plane Cavities"
Integrating Schematic Integrity Analysis Into Any Design Flow   Schematic integrity problems cause a lot of expensive PCB re-spins. Errors in schematics can lead to schedule delays, manufacturing reruns, support problems, and higher overall project costs. In this episode of Chalk Talk, Amelia Dalton chats with Craig Armenti from Mentor about how Xpedition Schematic Integrity Analysis can help catch and correct errors … Read More → "Integrating Schematic Integrity Analysis Into Any Design Flow"