EDA
Subscribe to EE Journal Daily Newsletter
5 + 1 =

A Second Pair of Eyes

We all know the drill. With fingers crossed and hopes held high, you send your board design off to manufacturing. Unless you’re the world’s most meticulous engineer, your design will get bounced back. In the process of fixing those pesky bugs, a whole lot more errors may work themselves into your original design. In this week’s episode of Fish Fry, we investigate … Read More → "A Second Pair of Eyes"

November 14, 2017
November 10, 2017
November 7, 2017
November 2, 2017
November 1, 2017
October 31, 2017
October 30, 2017
October 24, 2017
October 23, 2017
October 18, 2017
October 16, 2017
October 13, 2017
October 12, 2017
October 9, 2017
October 6, 2017
October 5, 2017
October 3, 2017
featured blogs
Nov 21, 2017
When plotting waveforms in Virtuoso Visualization and Analysis across sweeps you might want to group plots with the same values together, or display each corner in the same color etc. Of course, you can right-click on the plot and select Copy to or Move to and move the plots ...
Nov 20, 2017
When faced with the need for more of something, one possible solution is expansion. This could take many forms but one simple way is extending it to be greater in size, such as adding the dining room table leaves to fit more people around the Thanksgiving table. Samtec’s...
Nov 16, 2017
“Mommy, Daddy … Why is the sky blue?” As you scramble for an answer that lies somewhere between a discussion of refraction in gasses and “Oh, look—a doggie!” you already know the response to whatever you say will be a horrifyingly sincere “B...
Nov 07, 2017
Given that the industry is beginning to reach the limits of what can physically and economically be achieved through further shrinkage of process geometries, reducing feature size and increasing transistor counts is no longer achieving the same result it once did. Instead the...
chalk talks
Protium S1, the Most Productive FPGA-Based Prototyping SolutionFPGA-based prototypes are essential in most system designs today. But, building your own prototype is a challenging and expensive proposition. You need a robust solution with performance, scalability, software support, visibility, and a host of other important attributes. In this episode of Chalk Talk, Amelia Dalton chats with Juergen Jaeger about the Protium S1 FPGA-based … Read More → "Protium S1, the Most Productive FPGA-Based Prototyping Solution"
Cadence Xcelium Parallel Simulator: Third Generation Parallel VerificationGetting the best RTL simulation performance is a combination of improving single-core speed and cleverly partitioning the task so that parallel machines can give you the kind of performance boost you’d expect. In this episode of Chalk Talk, Amelia Dalton chats with Dave Lidrbauch from Cadence Design Systems about Xcelium – Cadence’s third-generation parallel RTL simulation … Read More → "Cadence Xcelium Parallel Simulator: Third Generation Parallel Verification"
Pegasus Verification System: Let Your DRC Fly!Design rule checking (DRC) can be the one of the biggest bottlenecks in getting a chip out the door. The computation power required for a large DRC run can be staggering. In this episode of Chalk Talk, Amelia Dalton chats with Christen Decoin from Cadence Design Systems about the Pegasus Verification System which will let your … Read More → "Pegasus Verification System: Let Your DRC Fly!"
JasperGold RTL Designer Signoff with Superlint and CDCRTL signoff is becoming the preferred design methodology for many teams today. But, verifying that your RTL will give you back the chip you want – the first time – is a challenging task. In this episode of Chalk Talk, Amelia Dalton chats with Pete Hardee of Cadence Design Systems about JasperGold, a comprehensive solution … Read More → "JasperGold RTL Designer Signoff with Superlint and CDC"
Tanner Designer: Analog VerificationMost design teams struggle with verification on the analog portion of their designs. While huge strides have been made in digital design over the past decade, analog design remains  more of a mystery for many engineers. In this episode of Chalk Talk, Amelia Dalton chats with Mass Sivilotti from Mentor about Tanner Designer – a … Read More → "Tanner Designer: Analog Verification"
Fixed Point, Floating Point – What Are the Needs of DSP Applications?When implementing DSP algorithms, the tradeoff between fixed- and floating-point math can have huge implications on performance and precision. In this episode of Chalk Talk, Amelia Dalton chats with Pushkar Patwardhan of Cadence Design Systems about making the critical decisions on floating-point versus fixed-point. Click here for more information about Tensilica Customizable Processor and DSP IP.