EDA
Subscribe Now

When Lives Depend on Your Machine-Learned Model

“How to validate training data is an open question that might be addressed by some combination of characterizing the data as well as the data generation or data collection process.”
‘Challenges in Autonomous Vehicle Testing and Validation’, Koopman and Wagner, 2016

Last summer, we published a piece on safety-critical capabilities in EDA. … Read More → "When Lives Depend on Your Machine-Learned Model"

Reality is Not Linear

At what point in the creation of a chip does physical design actually begin? (Spoiler Alert: answers may vary.) In this week’s episode of Fish Fry, Dave Stratman and I discuss the ongoing challenges of the physical design process, why convergent design flows are critical for today’s ever shrinking process nodes, and how form factor and the environment around the end customer affects physical design. We also … Read More → "Reality is Not Linear"

DVCon and the Big Data Problem

Design and verification technologies are front and center in this week’s episode of Fish Fry. DVCon General Chair Dennis Brophy joins us with a special sneak peak of the 2018 Design and Verification Conference. Dennis and I chat about how the biggest trends are reflected at DVCON, including machine learning, automotive technologies, and big data analysis. We also discuss the addition of shorter format workshops to … Read More → "DVCon and the Big Data Problem"

April 17, 2018
April 16, 2018
April 12, 2018
April 11, 2018
April 6, 2018
March 28, 2018
March 27, 2018
March 23, 2018
March 22, 2018
March 21, 2018
March 20, 2018
March 19, 2018
March 16, 2018
March 14, 2018
March 13, 2018
March 12, 2018
featured blogs
Apr 18, 2018
Standardization. COTS. Interoperability. Configurable. These often-used terms describe on-going efforts to define flexible and open critical embedded computing architectures. One such example is VITA-backed VPX. The goal of VPX is to leverage the latest switch fabric technolo...
Apr 18, 2018
Recently, the ESD Alliance organized the annual CEO Outlook panel with Simon, Wally, Grant and Dean. I covered the opening statements yesterday , but I figured it would get too long to put everything into a single post, so here's the rest of the evening. There's a b...
chalk talks
Integrating Schematic Integrity Analysis Into Any Design Flow   Schematic integrity problems cause a lot of expensive PCB re-spins. Errors in schematics can lead to schedule delays, manufacturing reruns, support problems, and higher overall project costs. In this episode of Chalk Talk, Amelia Dalton chats with Craig Armenti from Mentor about how Xpedition Schematic Integrity Analysis can help catch and correct errors … Read More → "Integrating Schematic Integrity Analysis Into Any Design Flow"
In-Design DFM Accelerates New Product Design and Introduction ProcessTaking your PCB from design into manufacturing can be a frustrating task. But, with the right up-front planning you can avoid schedule delays and headaches during the transition to production. In this episode of Chalk Talk, Amelia Dalton chats with Hemant Shah and Bryan LaPointe from Cadence Design Systems about DFM for board design. Click … Read More → "In-Design DFM Accelerates New Product Design and Introduction Process"
Mixed-Signal Digital Complexity Explosion   Mixed-signal design is becoming increasingly complex, and our old tools and methods just won’t cut it. In this episode of Chalk Talk, Amelia Dalton chats with Rod Metcalfe of Cadence Design Systems about the changing mixed-signal landscape and how Cadence’s robust suite of mixed-signal design solutions can solve your toughest problems. Click here … Read More → "Mixed-Signal Digital Complexity Explosion"
Moving Between FPGA and ASIC with High-Level Synthesis Writing RTL that works smoothly on both FPGA and ASIC implementations is nearly impossible. But, High-Level Synthesis (HLS) can make technology-independent design a breeze. In this episode of Chalk Talk, Amelia Dalton chats with Stuart Clubb of Mentor’s Catapult team about how to use HLS to accelerate your design flow. Click here for more … Read More → "Moving Between FPGA and ASIC with High-Level Synthesis"
Scaling Embedded Deep Learning Inference Performance with Dedicated Neural Network DSP   Neural networks are taking over a broad range of exciting applications these days. But, the amount of computation required for neural network inferencing can be daunting. In this episode of Chalk Talk, Amelia Dalton chats with Pulin Desai of Cadence Design Systems about some new processor IP designed specifically for neural network inferencing. … Read More → "Scaling Embedded Deep Learning Inference Performance with Dedicated Neural Network DSP"
IDesignSpec: Executable Register SpecificationGetting RTL right for your chip design is a difficult engineering and verification challenge with very high stakes. And, most of us use a variety of tools – including spreadsheets and text documents – to capture our design intent and details. In this episode of Chalk Talk, Amelia Dalton chats with Anupam Bakshi from Agnisys … Read More → "IDesignSpec: Executable Register Specification"