Gainesville, FL – March 19, 2024 –The 2024 Design and Verification Conference and Exhibition U.S. (DVCon U.S.), sponsored by Accellera Systems Initiative (Accellera), concluded its 36th annual event in San Jose, CA earlier this month. The 2024 Best Paper and Poster winners, as voted on by attendees, were announced during a reception in the exhibit hall on March 6.
Participants came from 28 countries and represented approximately 327 companies, with 394 attending the conference and exhibition for the first time. Overall attendance for DVCon U.S. 2024 was approximately 975, including attendees from 25 exhibiting companies.
“It was really an exciting time to be back at DVCon U.S.,” stated Tom Fitzpatrick, DVCon U.S. 2024 General Chair. “The camaraderie among industry peers created a lot of energy and interaction during the sessions and exhibition. We had many sessions that were standing room only. Artificial intelligence’s influence permeated presentations and discussions, underscoring DVCon’s commitment to empowering practicing engineers looking for ways to improve their day-to-day projects, as well as a look toward what will be impactful in the future.”
The award for the Stuart Sutherland Best Paper Presentation, as voted by conference attendees, went to Aman Kumar, Deepak Narayan Gadde, Thomas Nalapat, Evgenii Rezunov, and Fabio Cappellini, Infineon Technologies for their paper, “All Artificial, Less Intelligence: GenAI through the Lens of Formal Verification.” Second place was awarded to Neha Goyal and Justin Refice, Nvidia Corp. for “Leveraging Interface Classes to Improve UVM TLM.” William Moore, Paradigm Works took third place for his paper, “Gherkin Implementation in SystemVerilog Brings Agile Behavior-Driven Development to UVM.”
Top honors for best poster went to Sharada Vajja, Raghu Alamuri, Saksham Mehra, Google LLC for “AI-based Algorithms to Analyze and Optimize Performance Verification Efforts.” Nimay Shah, Pranav Dhayagude, and Paul Wright, Analog Devices Inc., and Raj Mitra, Cadence Design Systems, took second place for “Enabling True System-Level, Mixed-Signal Emulation.” Third place was awarded to Santosh Kumar, Yogish Raja, Geetika Agrawal, Karthikeyan SugumaranArjun Vazhayil, and Tommy Brunansky, Qualcomm Technologies Inc. for their poster “Scalable Functional Verification using Portable Stimulus Standard.”
Highlights of the Week:
- Accellera Day opened the conference on Monday featuring a morning tutorial on the Portable Test and Stimulus Standard (PSS), as well as 11 workshops throughout the day.
- The Accellera-sponsored luncheon on Monday focused on Federated Simulation and included a presentation from members of Accellera’s Federated Simulation Standard Proposed Working Group, including insights from Ford Motor Company.
- The keynote on Tuesday, “Addressing the Evolving Landscape of Automotive SoCs,” was presented by Paul Cunningham, senior vice president and general manager of the system & verification group of Cadence Design Systems and his guest, Anthony Hill, a Texas Instruments (TI) Fellow, who also leads the Technology Backplane Organization for TI’s Processors Business. They spoke to a standing room only crowd eager to learn more about the complexities and potential solutions for automotive design and verification.
- Wednesday morning opened with a panel: “When Will We Be Able to Say, ‘EDA GPT, Verify My ASIC’?” The topic provided for lively discussion among panelists about asking the right questions to get better output, what to do with code if it’s generated by someone else, etc. There was a long queue for those wanting to ask questions and learn more.
- On Wednesday afternoon Alex Starr, AMD Corporate Fellow responsible for AMD’s Shift Left Initiative and Verification Strategy, presented the second keynote, “From Chips to Checkered Flags: The Race Towards Real World Innovation.” He drew fascinating comparisons between designing a chip and a Formula 1 car.
- For the second consecutive year, the Poster Ninja Warrior Session determined the Stuart Sutherland Best Poster Award winners. The top four poster presenters engaged in a spirited battle in front of an audience helping to determine who would win top honors. Attendees enjoyed popcorn while listening to the presentations and questions from a panel of judges.
Save the date: DVCon U.S. 2025 will be held February 24-27 at the DoubleTree Hotel in San Jose, California. Tom Fitzpatrick will continue as General Chair for DVCon U.S. 2025.
About DVCon
DVCon is the premier conference for discussion of the functional design and verification of electronic systems. DVCon is sponsored by Accellera Systems Initiative, an independent, not-for-profit organization dedicated to creating design and verification standards required by systems, semiconductor, intellectual property (IP) and electronic design automation (EDA) companies. For more information about Accellera, please visit www.accellera.org. For more information about DVCon U.S., please visit here. Follow DVCon on Facebook, LinkedIn or @dvcon_us on Twitter or to comment, please use #dvcon_us.
